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DSPIC33FJ256MC710 Datasheet

  • DSPIC33FJ256MC710

  • 342頁

  • MICROCHIP   MICROCHIP

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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
5.2.1
SIX SERIAL INSTRUCTION
EXECUTION
5.2.2
REGOUT SERIAL INSTRUCTION
EXECUTION
The SIX control code allows execution of dsPIC33F/
PIC24H Programming Specification assembly instruc-
tions. When the SIX code is received, the CPU is sus-
pended for 24 clock cycles, as the instruction is then
clocked into the internal buffer. Once the instruction is
shifted in, the state machine allows it to be executed over
the next four clock cycles. While the received instruction
is executed, the state machine simultaneously shifts in
the next 4-bit command (see Figure 5-2).
Note 1:
Coming out of Reset, the first 4-bit control
code is always forced to SIX and a forced
NOP
instruction is executed by the CPU.
Five additional PGC clocks are needed
on start-up, thereby resulting in a 9-bit
SIX command instead of the normal 4-bit
SIX command. After the forced SIX is
clocked in, ICSP operation resumes as
normal (the next 24 clock cycles load the
first instruction word to the CPU).
2:
TBLRDH, TBLRDL, TBLWTH
and
TBLWTL
instructions must be followed by a
NOP
instruction.
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGD pin. After the REGOUT control code is
received, the CPU is held Idle for 8 cycles. After these
eight cycles, an additional 16 cycles are required to clock
the data out (see Figure 5-3).
The REGOUT code is unique because the PGD pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGD pin becomes an output as the VISI register is
shifted out.
Note:
Data is transmitted on the falling edge and
latched on the rising edge of PGC. For all
data transmissions, the Least Significant
bit (LSb) is transmitted first.
FIGURE 5-2:
1
PGC
P3
P2
PGD
0
0
0
0
2
3
4
SIX SERIAL EXECUTION
P1
5
6
7
8
9
P4
1
2
3
4
5
6
7
8
17 18
19 20
21
22 23 24
P4a
1
2
3
4
P1A
P1B
0
0
0
0
0
LSB X
X
X
X
X
X
X
X
X
X
X
X
X
X MSB
0
0
0
0
Execute PC 鈥?1,
Fetch SIX Control Code
24-Bit Instruction Fetch
Only for
Program
Memory Entry
PGD = Input
Execute 24-Bit Instruction,
Fetch Next Control Code
FIGURE 5-3:
1
PGC
2
3
REGOUT SERIAL EXECUTION
4
P4
1
2
7
8
1
2
3
4
5
6
11
12
13 14 15 16
P4a
1
2
3
4
P5
PGD
1
0
0
0
LSb
1
2
3
4
...
10 11
12 13 14 MSb
0
0
0
0
Execute Previous Instruction, CPU Held in Idle
Fetch REGOUT Control Code
PGD = Input
Shift Out VISI Register<15:0>
No Execution Takes Place,
Fetch Next Control Code
PGD = Input
PGD = Output
DS70152D-page 56
Preliminary
漏
2007 Microchip Technology Inc.

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