W681310
T
FS
F ST
T
F SR H
T
F SF H
T
F SR S
0
1
2
T
B D TD
3
4
5
6
T
B DTD
D5 D4
D3
D2
D1 D0
L SB
T
DRS
T
DRH
D5 D4
D3
D2
D1
D0
L SB
D7
M SB
7
8
9
T
H ID
10
11
12
13
14
T
BCK H
15
16
T
BCK L
17
18
T
H ID
D1 D0
L SB
T
DRS
D6
D5
T
DRH
D4 D3 D2
D1 D0
L SB
BCLK T
-1
T
B DTD
D7
M SB
D6
D5
T
T
B D T DB C K
D4 D3 D2
PC M T
D7
M SB
D6
PC M R
D7
M SB
D6
BCH = 0
B 1 C hannel
BCH = 1
B 2 C hannel
Figure 8.3 IDL PCM Timing
SYMBOL
1/T
FS
1/T
BCK
T
BCKH
T
BCKL
T
FSRH
T
FSRS
T
FSFH
T
BDTD
T
HID
DESCRIPTION
FST Frequency
BCLKT Frequency
BCLKT HIGH Pulse Width
BCLKT LOW Pulse Width
BCLKT 鈥? Falling Edge to FST Rising Edge
Hold Time
FST Rising Edge to BCLKT 0 Falling edge
Setup Time
BCLKT 0 Falling Edge to FST Falling Edge
Hold Time
BCLKT Rising Edge to Valid PCMT Delay
Time
Delay Time from the BCLKT 8 Falling Edge
(B1 channel) or BCLKT 18 Falling Edge (B2
Channel) to PCMT Output High Impedance
Valid PCMR to BCLKT Falling Edge Setup
Time
PCMR Hold Time from BCLKT Falling Edge
MIN
---
256
50
50
20
60
20
10
10
TYP
8
---
---
---
---
---
---
---
---
MAX
---
4800
---
---
---
---
---
60
50
UNIT
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
T
DRS
T
DRH
20
75
---
---
---
---
ns
ns
Table 8.3 IDL PCM Timing Parameters
- 17 -
Publication Release Date: September 2005
Revision B13