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AD5243 Datasheet

  • AD5243

  • Dual 256-Position I2C Compatible Digital Potentiometer

  • 22頁(yè)

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AD5243/AD5248
TIMING CHARACTERISTICS鈥擜LL VERSIONS
V
DD
= 5V 鹵 10%, or 3V 鹵 10%; V
A
= V
DD
; V
B
= 0 V; 鈭?0擄C < T
A
< +125擄C; unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
2
10
I C INTERFACE TIMING CHARACTERISTICS (Specifications Apply to All Parts)
SCL Clock Frequency
f
SCL
t
BUF
Bus Free Time between STOP and START
t
1
t
HD;STA
Hold Time (Repeated START)
t
2
After this period, the first clock pulse is
generated.
t
LOW
Low Period of SCL Clock
t
3
t
HIGH
High Period of SCL Clock
t
4
t
SU;STA
Setup Time for Repeated START Condition
t
5
11
t
HD;DAT
Data Hold Time
t
6
t
SU;DAT
Data Setup Time
t
7
t
F
Fall Time of Both SDA and SCL Signals
t
8
t
R
Rise Time of Both SDA and SCL Signals
t
9
t
SU;STO
Setup Time for STOP Condition
t
10
See notes at end of section.
Min
0
1.3
0.6
1.3
0.6
0.6
Typ
1
Max
400
Unit
kHz
碌s
碌s
碌s
碌s
碌s
碌s
ns
ns
ns
碌s
0.9
100
300
300
0.6
NOTES
1
2
Typical specifications represent average readings at 25擄C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (VW) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of 鹵1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
脳 V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagrams for locations of measured values.
11
The maximum t
HD:DAT
must be met only if the device does not stretch the low period (t
LOW
) of the SCL signal.
Rev. 0 | Page 5 of 20

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