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AD5243 Datasheet

  • AD5243

  • Dual 256-Position I2C Compatible Digital Potentiometer

  • 2063.45KB

  • 22頁

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AD5243/AD5248
Typical device-to-device matching is process lot dependent and
may vary by up to 鹵30%. Because the resistance element is
processed in thin film technology, the change in R
AB
with
temperature has a very low 35 ppm/擄C temperature coefficient.
340鈩?/div>
LOGIC
04109-0-015
GND
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
V
I
A
W
V
O
04109-0-014
Figure 39. ESD Protection of Digital Pins
A, B, W
04109-0-016
GND
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5243/AD5248 V
DD
and GND power supply defines the
boundary conditions for proper 3-terminal digital potentiome-
ter operation. Supply signals present on Terminals A, B, and W
that exceed V
DD
or GND are clamped by the internal forward
biased diodes (see Figure 41).
V
DD
B
Figure 38. Potentiometer Mode Configuration
A
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-
age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at V
W
with respect to ground for any valid input
voltage applied to terminals A and B is
D
256
鈭?/div>
D
V
W
(
D
)
=
V
A
+
V
B
256
256
W
B
04109-0-017
GND
Figure 41. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminals A, B, and W (see Figure 41), it is important to
power V
DD
/GND before applying any voltage to Terminals A, B,
and W; otherwise, the diode is forward biased such that V
DD
is
powered unintentionally and may affect the rest of the user鈥檚
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A
, V
B
, and V
W
. The relative
order of powering V
A
, V
B
, V
W
, and the digital inputs is not
important as long as they are powered after V
DD
/GND.
(3)
A more accurate calculation, which includes the effect of wiper
resistance, V
W
, is
V
W
(
D
)
=
R
(
D
)
R
WB
(
D
)
V
A
+
WA
V
B
R
AB
R
AB
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation overtemperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
WA
and R
WB
and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/擄C.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disk or chip ceramic capacitors
of 0.01 碌F to 0.1 碌F. Low ESR 1 碌F to 10 碌F tantalum or electro-
lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDA, SCL, AD0,
and AD1 (AD5248 only).
Rev. 0 | Page 14 of 20

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