最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

AD7687 Datasheet

  • AD7687

  • 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23

  • 30頁(yè)

  • AD

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

AD7940
SERIAL INTERFACE
Figure 20 shows the detailed timing diagram for serial interfac-
ing to the AD7940. The serial clock provides the conversion
clock and also controls the transfer of information from the
AD7940 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input.
The conversion is also initiated at this point and will require at
least 16 SCLK cycles to complete. Once 15 SCLK falling edges
have elapsed, the track-and-hold will go back into track mode
on the next SCLK rising edge as shown in Figure 20 at Point B.
On the 16th SCLK falling edge, the SDATA line will go back
into three-state. If the rising edge of CS occurs before 16 SCLKs
have elapsed, the conversion will be terminated and the SDATA
line will go back into three-state; otherwise SDATA returns to
three-state on the 16th SCLK falling edge as shown in Figure 20.
Sixteen serial clock cycles are required to perform the conver-
sion process and to access data from the AD7940. CS going low
provides the first leading zero to be read in by the microcontroller
or DSP. The remaining data is then clocked out by subsequent
SCLK falling edges beginning with the second leading zero, thus
the first falling clock edge on the serial clock has the first leading
zero provided and also clocks out the second leading zero. The
data transfer will consist of two leading zeros followed by the 14
bits of data. The final bit in the data transfer is valid on the 16th
falling edge, having been clocked out on the previous (15th)
falling edge.
It is also possible to take valid data on each SCLK rising edge
rather than falling edge, since the SCLK cycle time is long
enough to ensure the data is ready on the rising edge of SCLK.
However, the first leading zero will still be driven by the CS
falling edge, and so it can be taken only on the first SCLK falling
edge. It may be ignored, and the first rising edge of SCLK after
the CS falling edge would have the second leading zero pro-
vided and the 15th rising SCLK edge would have DB0 provided.
This method may not work with most microcontrollers/DSPs, but
could possibly be used with FPGAs and ASICs.
CS
t
2
SCLK
1
2
3
4
t
6
t
CONVERT
B
5
13
14
15
16
t
7
t
3
SDATA
3-STATE
0
ZERO
DB13
DB12
t
5
DB2
DB1
DB0
t
8
t
QUIET
3-STATE
03305-0-013
t
4
DB11
DB10
2 LEADING ZEROS
Figure 20. AD7940 Serial Interface Timing Diagram
Rev. 0 | Page 16 of 20

AD7687相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門(mén)IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！