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AD8000

OUTLINE DIMENSIONS

5.00 (0.197)

4.90 (0.193)

4.80 (0.189)

8

1

5

4

BOTTOM VIEW

(PINS UP)

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

2.29 (0.092)

6.20 (0.244)

6.00 (0.236)

5.80 (0.228)

2.29 (0.092)

TOP VIEW

1.27 (0.05)

BSC

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

SEATING

0.10

PLANE

1.75 (0.069)

1.35 (0.053)

0.50 (0.020)

脳

45擄

0.25 (0.010)

0.51 (0.020)

0.31 (0.012)

8擄

0.25 (0.0098) 0擄 1.27 (0.050)

0.40 (0.016)

0.17 (0.0068)

COMPLIANT TO JEDEC STANDARDS MS-012

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 54. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body (RD-8-1)

Dimensions shown in millimeters and (inches)

3.00

BSC SQ

0.45

0.60 MAX

0.50

0.40

0.30

PIN 1

INDICATOR

8

1

PIN 1

INDICATOR

TOP

VIEW

2.75

BSC SQ

0.50

BSC

5

(BOTTOM VIEW)

EXPOSED

PAD

1.50

REF

4

1.90

1.75

1.60

0.90

0.85

0.80

12擄 MAX

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.30

0.23

0.18

0.20 REF

0.25

MIN

1.60

1.45

1.30

SEATING

PLANE

Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm 脳 3 mm Body (CP-8-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD8000YRDZ

1

AD8000YRDZ-REEL

1

AD8000YRDZ-REEL7

1

AD8000YCPZ-R2

1

AD8000YCPZ-REEL

1

AD8000YCPZ-REEL7

1

Minimum Ordering Quantity

1

2,500

1,000

250

5,000

1,500

Temperature Range

鈥?0擄C to +125擄C

鈥?0擄C to +125擄C

鈥?0擄C to +125擄C

鈥?0擄C to +125擄C

鈥?0擄C to +125擄C

鈥?0擄C to +125擄C

Package Description

8-Lead SOIC/EP

8-Lead SOIC/EP

8-Lead SOIC/EP

8-Lead LFCSP

8-Lead LFCSP

8-Lead LFCSP

Branding

Package Option

RD-8-1

RD-8-1

RD-8-1

CP-8-2

CP-8-2

CP-8-2

HNB

HNB

HNB

1

Z = Pb-free part.

Rev. 0 | Page 17 of 20

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