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AD8381 Datasheet

  • AD8381

  • Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decim...

  • 17頁

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AD8381
FUNCTIONAL DESCRIPTION
The AD8381 is a system building block designed to directly
drive the columns of LCD panels of the type popularized for use
in data projectors. It comprises six channels of precision 10-bit
digital-to-analog converters loaded from a single, high-speed,
10-bit-wide input. Precision current feedback amplifiers, provid-
ing well-damped pulse response and rapid voltage settling into
large capacitive loads, buffer the six outputs. Laser trimming at
the wafer level ensure low absolute output errors and tight channel-
to-channel matching. In addition, tight part-to-part matching
in high channel count systems is guaranteed by the use of an
external voltage reference.
INPUT DATA LOADING (STart SeQuence Control)
Channel 5 and proceeds to Channel 0 when the R/L input is
held LOW.
DATA TRANSFER TO OUTPUTS (XFR Control)
Data transfer to all outputs is initiated by the XFR control input.
When XFR is held HIGH during a rising CLK edge, data is
simultaneously transferred to all outputs on the immediately
following falling CLK edge.
VCOM REFERENCE (VMID Reference Input)
An external analog reference voltage connected to this input sets
the reference level at the outputs. This input is normally con-
nected to VCOM.
FULL-SCALE OUTPUT (VREFHI, VREFLO Reference
Inputs)
A valid STSQ control input initiates a new six-clock pulse loading
cycle, during which six input data-words are loaded sequentially
into six internal channels. A new loading sequence begins on the
current active CLK edge only when STSQ was held HIGH at
the preceding active CLK edge.
DATA LOADING鈥擡XPANDED SYSTEMS (Even/Odd
Control)
The difference between two external analog reference voltages,
connected to these inputs, sets the full-scale output voltage at
the outputs. VREFLO is normally tied to VMID.
ANALOG VOLTAGE INVERSION (INVert Control)
To facilitate expanded, even/odd systems, the active CLK edge, at
which input data is loaded, is set with the E/O control input.
Input data is loaded on rising CLK edges while the E/O input is
held HIGH and loaded on falling CLK edges while the E/O
input is held LOW.
DATA LOADING鈥擨NVERTED IMAGES (Right/Left
Control)
To facilitate systems that use column, row or pixel inversion,
the analog output voltage inversion is controlled by the INV
control input. While INV is HIGH, the analog voltage equiva-
lent of the input code is subtracted from (VMID + VFS) at each
output. While INV is LOW, the analog voltage equivalent of the
input code is added to (VMID 鈥?VFS) at each output.
STANDBY MODE (STBY Control)
To facilitate image mirroring, the order in which input data is
loaded is set with the R/L input.
A new loading sequence begins at Channel 0 and proceeds to
Channel 5 when the R/L input is held HIGH and begins at
A HIGH applied to the STBY input debiases the internal
circuitry, dropping the quiescent power dissipation to a few
milliwatts. Since both digital and analog circuits are debiased,
all stored data will be lost. Upon returning STBY to LOW,
normal operation is restored.
鈥?0鈥?/div>
REV. 0

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