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AD9381 Datasheet

  • AD9381

  • HDMI? Display Interface

  • 1745.21KB

  • 45頁

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AD9381
DESIGN GUIDE
GENERAL DESCRIPTION
The AD9381 is a fully integrated solution for receiving DVI/
HDMI signals and is capable of decoding HDCP-encrypted
signals through connections to an internal EEPROM. The
circuit is ideal for providing an interface for HDTV monitors
or as the front end to high performance video scan converters.
Implemented in a high performance CMOS process, the
interface can capture signals with pixel rates of up to 150 MHz.
The AD9381 includes all necessary circuitry for decoding
TMDS signaling including those encrypted with HDCP. The
output data formatting includes a color space converter (CSC),
which accommodates any input color space and can output any
color space. All controls are programmable via a 2-wire serial
interface. Full integration of these sensitive mixed signal
functions makes system design straight-forward and less
sensitive to the physical and electrical environment.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. However, it is
tolerant of 5 V logic signals.
OUTPUT SIGNAL HANDLING
The digital outputs operate from 1.8 V to 3.3 V (V
DD
).
Power Management
The AD9381 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, the
power-down bit, and the power-down pin to determine the
correct power state. There are four power states: full-power,
seek mode, auto power-down, and power-down.
Table 7 summarizes how the AD9381 determines which power
mode to use and which circuitry is powered on/off in each of
these modes. The power-down command has priority and then
the automatic circuitry. The power-down pin (Pin 81鈥攑olarity
set by Register 0x26[3]) can drive the chip into four power-
down options. Bit 2 and Bit1 of Register 0x26 control these four
options. Bit 0 controls whether the chip is powered down or the
outputs are placed in high impedance mode (with the exception
of SOG). Bit 7 to Bit 4 of Register 0x26 control whether the
outputs, SOG, Sony Philips digital interface (S/PDIF ) or Inter-
IC sound bus (I
2
S or IIS) outputs are in high impedance mode
or not. See the 2-Wire Serial Control Register Detail section for
more details.
DIGITAL INPUTS
The digital control inputs (I
2
C) on the AD9381 operate to 3.3 V
CMOS levels. In addition, all digital inputs, except the TMDS
(HDMI/DVI) inputs, are 5 V tolerant (applying 5 V to them
does not cause damage). The TMDS input pairs (Rx0+/Rx0鈭?
Rx1+/Rx1鈭? Rx2+/Rx2鈭? and RxC+/RxC鈭? must maintain a
100 惟 differential impedance (through proper PCB layout)
from the connector to the input where they are internally
terminated (50 惟 to 3.3 V). If additional ESD protection is
desired, use of a California Micro Devices (CMD) CM1213
(among others) series low capacitance ESD protection offers
8 kV of protection to the HDMI TMDS lines.
Table 7. Power-Down Mode Descriptions
Mode
Full Power
Seek Mode
Seek Mode
Power-Down
1
2
Power-Down
1
1
1
0
1
Inputs
Sync Detect
2
1
0
0
X
Auto PD Enable
3
X
0
1
Power-On or Comments
Everything
Everything
Serial bus, sync activity detect, SOG, band gap reference
Serial bus, sync activity detect, SOG, band gap reference
Power-down is controlled via Bit 0 in Serial Bus Register 0x26.
Sync detect is determined by OR鈥檌ng Bits 7 to Bit 2 in Serial Bus Register 0x15.
3
Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27.
Rev. 0 | Page 9 of 44

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