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AD9381 Datasheet

  • AD9381

  • HDMI? Display Interface

  • 1745.21KB

  • 45頁

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AD9381
0x33鈥擝it[7] Macrovision Detect Mode
0 = standard definition. 1 = progressive scan mode.
0x35鈥擝its[6:5] Color Space Converter Mode
These two bits set the fixed point position of the CSC
coefficients, including the A4, B4, and C4 offsets.
Table 17. CSC Fixed Point Converter Mode
Select
00
01
1脳
Result
鹵1.0, 鈭?096 to +4095
鹵2.0, 鈭?192 to +8190
鹵4.0, 鈭?6384 to +16380
0x33鈥擝it[6] Macrovision Settings Override
This defines whether preset values are used for the MV line
counts and pulse widths or the values stored in I
2
C registers.
0 = use hard-coded settings for line counts and pulse widths.
1 = use I
2
C values for these settings.
0x33鈥擝its[5:0] Macrovision Line Count End
Set the end line for Macrovision detection. Along with
Register 0x32, Bits [5:0], they define the region where MV
pulses are expected to occur. The power-up default is Line 21.
0x35鈥擝its[4:0] Color Space Conversion Coefficient A1
MSBs
These 5 bits form the 5 MSBs of the Color Space Conversion
Coefficient A1. This, combined with the 8 LSBs of the following
register, form a 13-bit, twos complement coefficient which is
user programmable. The equation takes the form of:
R
OUT
= (A1 脳 R
IN
) + (A2 脳 G
IN
) + (A3 脳 B
IN
) + A4
G
OUT
= (B1 脳 R
IN
) + (B2 脳 G
IN
) + (B3 脳 B
IN
) + B4
B
OUT
= (C1 脳 R
IN
) + (C2 脳 G
IN
) + (C3 脳 B
IN
) + C4
The default value for the 13-bit, A1 coefficient is 0x0C52.
0x34鈥擝its[7:6] Macrovision Pulse Limit Select
Set the number of pulses required in the last three lines (SD
mode only). If there is not at least this number of MV pulses,
the engine stops. These 2 bits define these pulse counts:
00 = 6
01 = 4
10 = 5 (default)
11 = 7
0x34鈥擝it[5] Low Frequency Mode
Sets the audio PLL to low frequency mode. Low frequency
mode should only be set for pixel clocks < 80 MHz.
0x36鈥擝its[7:0] Color Space Conversion Coefficient A1
LSBs
See the Register 0x35 section.
0x34鈥擝it[4] Low Frequency Override
Allows the previous bit to be used to set low frequency mode
rather than the internal auto-detect.
0x37鈥擝its[4:0] CSC A2 MSBs
These five bits form the 5 MSBs of the Color Space Conversion
Coefficient A2. Combined with the 8 LSBs of the following
register, they form a 13-bit, twos complement coefficient that is
user programmable. The equation takes the form of:
R
OUT
= (A1 脳 R
IN
) + (A2 脳 G
IN
) + (A3 脳 B
IN
) + A4
G
OUT
= (B1 脳 R
IN
) + (B2 脳 G
IN
) + (B3 脳 B
IN
) + B4
B
OUT
= (C1 脳 R
IN
) + (C2 脳 G
IN
) + (C3 脳 B
IN
) + C4
The default value for the 13-bit, A2 coefficient is 0x0800.
0x34鈥擝it[3] Up Conversion Mode
0 = repeat Cb/Cr values. 1 = interpolate Cb/Cr values.
0x34鈥擝it[2] CbCr Filter Enable
Enables the FIR filter for 4:2:2 CbCr output.
COLOR SPACE CONVERSION
The default power-up values for the color space converter
coefficients (R0x35 through R0x4C) are set for ATSC RGB-to-
YCbCr conversion. They are completely programmable for
other conversions.
0x38鈥擝its[7:0] CSC A2 LSBs
See the Register 0x37 section.
0x39鈥擝its[4:0] CSC A3 MSBs
The default value for the 13-bit A3 is 0x0000.
0x34鈥擝it[1] Color Space Converter Enable
This bit enables the color space converter. 0 = disable color
space converter. 1 = enable color space converter. The power-up
default setting is 0.
0x3A鈥擝its[7:0] CSC A3 LSBs
0x3B鈥擝its[4:0] CSC A4 MSBs
The default value for the 13-bit A4 is 0x19D7.
0x3C鈥擝its[7:0] CSC A4 LSBs
0x3D鈥擝its[4:0] CSC B1 MSBs
The default value for the 13-bit B1 is 0x1C54.
0x3E鈥擝its[7:0] CSC B1 LSBs
0x3F鈥擝its[4:0] CSC B2 MSB
The default value for the 13-bit B2 is 0x0800.
Rev. 0 | Page 30 of 44

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