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AD9381 Datasheet

  • AD9381

  • HDMI? Display Interface

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AD9381
Hex
Address
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
Read/Write
or Read Only
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Default Value
Register Name
ISRC1_PB8
ISRC1_PB9
ISRC1_PB10
ISRC1_PB11
ISRC1_PB12
NDF
ISRC1_PB13
ISRC1_PB14
ISRC1_PB15
ISRC1_PB16
ISRC2 Packet Byte 0
Description
ISRC1_PB8.
ISRC1_PB9.
ISRC1_PB10.
ISRC1_PB11.
ISRC1_PB12.
New data flags (see 0x87).
ISRC1_PB13.
ISRC1_PB14.
ISRC1_PB15.
ISRC1_PB16.
ISRC2 Packet Byte 0 (ISRC2_PB0). This is transmitted
only when the ISRC_ continue bit (Register 0xC8,
Bit 7) is set to 1.
ISRC2_PB1.
ISRC2_PB2.
New data flags (see 0x87).
ISRC2_PB3.
ISRC2_PB4.
ISRC2_PB5.
ISRC2_PB6.
ISRC2_PB7.
ISRC2_PB8.
ISRC2_PB9.
New data flags (see 0x87).
ISRC2_PB10.
ISRC2_PB11.
ISRC2_PB12.
ISRC2_PB13.
ISRC2_PB14.
ISRC2_PB15.
ISRC2_PB16.
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
[7:0]
[7:0]
[6:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
ISRC2_PB1
ISRC2_PB2
New Data Flags
ISRC2_PB3
ISRC2_PB4
ISRC2_PB5
ISRC2_PB6
ISRC2_PB7
ISRC2_PB8
ISRC2_PB9
New Data Flags
ISRC2_PB10
ISRC2_PB11
ISRC2_PB12
ISRC2_PB13
ISRC2_PB14
ISRC2_PB15
ISRC2_PB16
Rev. 0 | Page 25 of 44

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