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AD9381 Datasheet

  • AD9381

  • HDMI? Display Interface

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AD9381
Hex
Address
0x43
0x44
Read/Write
or Read Only
Read/Write
Read/Write
Bits
[4:0]
[7:0]
Default Value
***00010
10010010
Register Name
CSC_Coeff_B4 MSB
CSC_Coeff_B4 LSB
Description
MSB, Register 0x44.
CSC coefficient for equation:
R
OUT
= (A1 脳 R
IN
) + (A2 脳 G
IN
) + (A3 脳 B
IN
) + A4
G
OUT
= (B1 脳 R
IN
) + (B2 脳 G
IN
) + (B3 脳 B
IN
) +
B4
B
OUT
= (C1 脳 R
IN
) + (C2 脳 G
IN
) + (C3 脳 B
IN
) + C4
MSB, Register 0x46.
CSC coefficient for equation:
R
OUT
= (A1 脳 R
IN
) + (A2 脳 G
IN
) + (A3 脳 B
IN
) + A4
G
OUT
= (B1 脳 R
IN
) + (B2 脳 G
IN
) + (B3 脳 B
IN
) + B4
B
OUT
= (C1 脳 R
IN
) + (C2 脳 G
IN
) + (C3 脳 B
IN
) + C4
MSB, Register 0x48.
CSC coefficient for equation:
R
OUT
= (A1 脳 R
IN
) + (A2 脳 G
IN
) + (A3 脳 B
IN
) + A4
G
OUT
= (B1 脳 R
IN
) + (B2 脳 G
IN
) + (B3 脳 B
IN
) + B4
B
OUT
= (C1 脳 R
IN
) + (C2 脳 G
IN
) + (C3 脳 B
IN
) + C4
MSB, Register 0x4A.
CSC coefficient for equation:
R
OUT
= (A1 脳 R
IN
) + (A2 脳 G
IN
) + (A3 脳 B
IN
) + A4
G
OUT
= (B1 脳 R
IN
) + (B2 脳 G
IN
) + (B3 脳 B
IN
) + B4
B
OUT
= (C1 脳 R
IN
) + (C2 脳 G
IN
) + (C3 脳 B
IN
) + C4
MSB, Register 0x4C.
CSC coefficient for equation:
R
OUT
= (A1 脳 R
IN
) + (A2 脳 G
IN
) + (A3 脳 B
IN
) + A4
G
OUT
= (B1 脳 R
IN
) + (B2 脳 G
IN
) + (B3 脳 B
IN
) + B4
B
OUT
= (C1 脳 R
IN
) + (C2 脳 G
IN
) + (C3 脳 B
IN
) +
C4
Must be written to 0x20 for proper operation.
Must be written to default of 0x0F for proper
operation.
A1 overrides the AV mute value with Bit 6.
Sets AV mute value if override is enabled.
Disables mute of video during AV mute.
Disables mute of audio during AV mute.
MCLK PLL enable鈥攗ses analog PLL.
MCLK PLL N [2:0]鈥攖his controls the division of the
MCLK out of the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4,
etc.
Prevents the N/CTS packet on the link from writing
to the N and CTS registers.
Controls the multiple of 128 Fs, used for MCLK out .
0 = 128 f
S
, 1 = 256 f
S
, 2 = 384, 7 = 1024 f
S
.
This disables the MDA/MCL pull-ups.
Clock termination power-down override: 0 = auto,
1 = manual.
Clock termination: 0 = normal, 1 = disconnected.
This bit resets the audio FIFO if underflow is
detected.
This bit resets the audio FIFO if overflow is
detected.
This bit three-states the MDA/MCL lines.
0x45
0x46
Read/Write
Read/Write
[4:0]
[7:0]
***00000
00000000
CSC_Coeff_C1 MSB
CSC_Coeff_C1 LSB
0x47
0x48
Read/Write
Read/Write
[4:0]
[7:0]
***01000
00000000
CSC_Coeff_C2 MSB
CSC_Coeff_C2 LSB
0x49
0x4A
Read/Write
Read/Write
[4:0]
[7:0]
***01110
10000111
CSC_Coeff_C3 MSB
CSC_Coeff_C3 LSB
0x4B
0x4C
Read/Write
Read/Write
[4:0]
[7:0]
***11000
10111101
CSC_Coeff_C4 MSB
CSC_Coeff_C4 LSB
0x50
0x56
0x57
Read/Write
Read/Write
Read/Write
[7:0]
[7:0]
[7]
[6]
[3]
[2]
[7]
[6:4]
00100000
00001111
0*******
*0******
****0***
*****0**
Test
Test
A/V Mute Override
AV Mute Value
Disable Video Mute
Disable Audio Mute
MCLK PLL Enable
MCLK PLL_N
0x58
Read/Write
[3]
[2:0]
0x59
Read/Write
[6]
[5]
[4]
[2]
[1]
[0]
N_CTS_Disable
MCLK FS_N
MDA/MCL PU
CLK Term O/R
Manual CLK Term
FIFO Reset UF
FIFO Reset OF
MDA/MCL Three-State
Rev. 0 | Page 18 of 44

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