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AD9381 Datasheet

  • AD9381

  • HDMI? Display Interface

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AD9381
AUDIO BOARD LEVEL MUTING
The audio can be muted through the infoframes or locally
via the serial bus registers. This can be controlled with
Register R0x57, Bits [7:4].
This information is the fundamental difference between DVI
and HDMI transmissions and is located in read-only registers
R0x5A to R0xEE. In addition to this information, registers are
provided to indicate that new information has been received.
Registers with addresses ending in 0xX7 or 0xXF beginning at
R0x87 contain the new data flags (NDF) information. All of
these registers contain the same information and all are reset
once any of them are read. Although there is no external
interrupt signal, it is easy for the user to read any of these
registers and see if there is new information to be processed.
AVI Infoframes
The HDMI TMDS transmission contains Infoframes with
specific information for the monitor such as:
鈥?/div>
Audio information
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
2 to 8 channels of audio identified
Audio coding
Audio sampling frequency
OUTPUT DATA FORMATS
The AD9398 supports 4:4:4, 4:2:2, double data-rate (DDR),
and BT656 output formats. Register 0x25[3:0] controls the
output mode. These modes and the pin mapping are shown
in Table 10.
Speaker placement
N and CTS values (for reconstruction of the audio)
Muting
Source information
鈥?/div>
鈥?/div>
鈥?/div>
CD
SACD
DVD
鈥?/div>
Video information
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Video ID code (per CEA861B)
Color space
Aspect ratio
Horizontal and vertical bar information
MPEG frame information (I, B, or P frame)
鈥?/div>
Vendor (transmitter source) name and product model
.
Table 10.
Port
Bit
4:4:4
4:2:2
4:4:4 DDR
4:2:2 to 12
1
Red
7
6
5
4
Red/Cr [7:0]
CbCr [7:0]
DDR
鈫?/div>
1
G [3:0]
DDR
鈫?/div>
R [7:0]
CbCr [11:0]
3
2
1
0
DDR
鈫?/div>
B [7:4]
Green
7
6
5
4
Green/Y [7:0]
Y [7:0]
DDR
鈫?/div>
B [3:0]
DDR
鈫?/div>
G [7:4]
Blue
3
2
1
0
7
6
5
4
3
Blue/Cb [7:0]
DDR 4:2:2
鈫?/div>
CbCr
鈫?/div>
Y, Y
DDR 4:2:2
鈫?/div>
CbCr [11:0]
DDR 4:2:2
鈫?/div>
Y,Y [11:0]
Y [11:0]
2
1
0
Arrows in the table indicate clock edge. Rising edge of clock =
鈫?
falling edge =
鈫?
Rev. 0 | Page 13 of 44

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