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AD74111 Datasheet

  • AD74111

  • Low Cost, Low Power Mono Audio Codec

  • 22頁

  • AD

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AD74111
t
FS
DFS
t
FH
DCLK
t
CH
t
CL
MSB
MSB鈥?
MSB鈥?
t
FD
DIN
t
DS
t
DH
DOUT
MSB
MSB鈥?
MSB鈥?
t
DD
Figure 11. Serial Port (SPORT) Timing
Serial Port Operating Modes
Master Mode Operation
The serial port of the AD74111 can be programmed to operate
in a variety of modes depending on the requirements and flex-
ibility of the DSP to which it is connected. The two principal
modes of operation are Mixed mode and Data mode.
Mixed Mode
In Master mode, the DFS and DCLK pins are outputs from the
AD74111. This is the easiest mode in which to use the AD74111
because the correct timing relationship between sample rate,
DCLK, and DFS is controlled by the AD74111.
Slave Mode Operation
Mixed mode allows the control registers of the AD74111 to be
programmed and read back. It also allows data to be sent to the
DACs and data to be read from the ADCs. In Mixed mode,
there are separate data slots, each with its own frame synchroni-
zation signal (DFS) for control and DAC or ADC information.
The AD74111 powers up in Mixed mode by default to allow
the control registers to be programmed. Figure 13 shows the
default setting for Mixed mode.
Data Mode
Data mode can be used when programming or reading the
control registers is no longer required. Data mode provides a
frame synchronization (DFS) pulse for each sample of data.
Once the part has been programmed into Data mode, the only
way to change the control registers is to perform a hardware reset
to put the AD74111 back into Mixed mode. Figure 15 shows
the default setting for Data mode.
Data-Word Length
In Slave mode, the DFS and DCLK pins are inputs to the
AD74111. Care needs to be exercised when designing a system
to operate the AD74111 in this mode as the relationship between
the sample rate, DCLK, and DFS needs to be controlled by the
DSP or other controller and must be compatible with the inter-
nal DAC/ADC engine of the AD74111. Figure 12 shows a block
diagram of the DAC engine and the AD74111鈥檚 serial port. The
sample rate for the DAC engine is determined by the MCLK
and MCLK prescalers. The DAC engine will read data from the
DAC Data register at this rate. It is therefore important that the
serial port is updated at the same rate, as any error between the
two will accumulate and eventually cause the DAC engine to have
to resynchronize with the serial port, which will cause erroneous
values on the DAC output pins.
RESYNC*
DAC ENGINE
LOAD DAT
VOUT
The AD74111 can be programmed to send DAC audio data
and receive ADC audio data in different word length formats of
16, 20, or 24 bits. The default mode is 16 bits, but this can be
changed by programming Control Register C for the appropriate
word length.
Selecting Master or Slave Mode
DFS
DIN
DAC DATA REGISTER
SERIAL PORT
*RESYNC
IS ONLY USED WHEN THE DAC BECOMES
UNSYNCHRONIZED WITH THE SERIAL PORT
The initial operating mode of the AD74111 is determined by
the state of the DIN pin following a reset. If the DIN pin is high
during this time, Slave mode is selected. In Slave mode, the
DFS and DCLK pins are inputs and the control signals for
these pins must be provided by the DSP or other controller. If
the DIN pin is low immediately following a reset, the AD74111
will operate in Master mode.
Figure 12. DAC Engine
In most cases, it is easy to keep a DSP in synchronization with
the AD74111 if they are both run from the same clock or the
DSP clock is a multiple of the AD74111鈥檚 MCLK. In this case,
REV. 0
鈥?1鈥?/div>

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