ADCMP580/ADCMP581/ADCMP582
TYPICAL APPLICATION CIRCUITS
GND
V
TP
V
IN
V
P
V
N
V
TN
50惟
50惟
Q
V
P
V
N
ADCMP580
CML
ADCMP580
Q
1.5k惟
50惟
50惟
04672-025
LATCH
INPUTS
Figure 17. Zero-Crossing Detector with CML Outputs
04672-020
V
EE
Figure 21. Disabling the Latch Feature on the ADCMP580
V
TP
V
P
V
N
V
TN
50惟
V
TT
LATCH
INPUTS
50惟
V
P
V
N
Q
ADCMP581
Q
V
P
V
N
ADCMP581
50惟
450惟
RSECL
50惟
04672-023
04672-021
V
TT
V
EE
Figure 18. LVDS to a 50 惟 Back-Terminated (RS) ECL Receiver
Figure 22. Disabling the Latch Feature on the ADCMP581
ADCMP580
HYS
V
P
V
N
ADCMP582
RSPECL
04672-026
0惟 TO 5k惟
50惟
50惟
1k惟
50惟
50惟
04672-027
V
EE
V
TT
Figure 19. Adding Hysteresis Using the HYS Control
Figure 23. Disabling the Latch Feature on the ADCMP582
GND
50惟
V
IN
V
TH
+
50惟
Q
Q
ADCMP580
鈥?/div>
Figure 20. Comparator with 鈭? to +3 V Input Range
04672-022
LATCH
INPUTS
Rev. 0 | Page 10 of 16
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