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ADP3422 Datasheet

  • ADP3422

  • IMVP-II-Compliant Core Power Controller for Mobile CPUs

  • 473.47KB

  • 17頁(yè)

  • AD

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ADP3422鈥揝PECIFICATIONS
(continued)
Parameter
LOW-SIDE DRIVE CONTROL
Output Voltage (CMOS Output)
Output Current
Symbol
V
DRVLSD
I
DRVLSD
Conditions
DPRSLP = H
DPRSLP = L
V
DRVLSD
= 1.5 V
DPRSLP = L
DPRSLP = H
Min
Typ
Max
0.4
V
CC
Unit
V
V
mA
mA
0.7 V
CC
+0.4
鈥?.4
OVER/REVERSE VOLTAGE
PROTECTION
Over-Voltage Threshold
Reverse-Voltage Threshold
V
COREFB,OVP
V
COREFB,RVP
Output Current (Open Drain Output) I
CLAMP
V
COREFB
Rising
V
COREFB
Falling
V
COREFB
Falling
V
COREFB
Rising
V
CLAMP
= 1.5 V
V
COREFB
= 2.2 V
V
COREFB
= V
DACOUT
= 1.25 V 1
2.0
1.8
鈥?.3
鈥?.05
2.2
V
V
V
V
碌A(chǔ)
mA
10
4
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Two test conditions:
1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V
COREFB,BAD
= 1.0 V at V
VID
= 1.25 V setting) to the COREFB pin right
after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time.
2. PWRGD is forced to fail (V
COREFB,BAD
= 1.0 V at V
VID
= 1.25 V setting) but gets into the CoreGood-window (V
COREFB,GOOD
= 1.25 V) right after the moment that
BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time.
3
Guaranteed by characterization.
4
Measured from 50% of VID code transition amplitude to the point where V
DACOUT
settles within
鹵
1% of its steady state value.
5
40 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
6
Measured between the 30% and 70% points of the output voltage swing.
Specifications subject to change without notice.
鈥?鈥?/div>
REV. 0

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