AD5547/AD5557
Table 5. Address Decoder Pins
A1
0
0
1
1
A0
0
1
0
1
Output Update
DAC A
None
DAC A and B
DAC B
Table 6. Control Inputs
RS
0
1
1
1
1
1
WR
X
0
1
0
LDAC
X
0
1
1
Register Operation
Reset the output to 0 with MSB pin = 0; reset the output to midscale with MSB pin = 1.
Load the input register with data bits.
Load the DAC register with the contents of the input register.
The input and DAC registers are transparent.
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse, and are then loaded into the DAC register on the rising edge of the pulse.
No register operation.
1
0
Rev. 0 | Page 8 of 20