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AD5547 Datasheet

  • AD5547

  • Dual Current Output, Parallel Input, 16-/14-Bit Multiplying ...

  • 22頁

  • AD

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AD5547/AD5557
DIGITAL SECTION
The AD5547/AD5557 have 16-/14-bit parallel inputs. The
devices are double-buffered with 16-/14-bit registers. The dou-
ble-buffered feature allows the simultaneous update of several
AD5547/AD5557s. For the AD5547, the input register is loaded
directly from a 16-bit controller bus when WR is brought low.
The DAC register is updated with data from the input register
when LDAC is brought high. Updating the DAC register
updates the DAC output with the new data (see Figure 19). To
make both registers transparent, tie WR low and LDAC high.
The asynchronous RS pin resets the part to zero scale if the
MSB pin = 0, and to midscale if the MSB pin = 1.
The voltage reference temperature coefficient and long-term
drift are primary considerations. For example, a 5 V reference
with a TC of 5 ppm/擄C means the output changes by 25 碌V/擄C.
As a result, a reference operating at 55擄C contributes an
additional 750 碌V full-scale error.
Similarly, the same 5 V reference with a 鹵50 ppm long-term
drift means the output may change by 鹵250 碌V over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
PCB LAYOUT, POWER SUPPLY BYPASSING, AND
GROUND CONNECTIONS
It is a good practice to employ a compact, minimum-lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
The PCB metal traces between V
REF
and R
FB
should also be
matched to minimize gain error.
It is also essential to bypass the power supply with quality
capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 碌F to 0.1 碌F disc or chip ceramic
capacitors. Low ESR 1 碌F to 10 碌F tantalum or electrolytic
capacitors should also be applied at the supply in parallel with
the ceramic capacitor to minimize transient disturbance and
filter out low frequency ripple.
To minimize the digital ground bounce, the AD5547/AD5557
DGND terminal should be joined with the AGND terminal at a
single point. Figure 21 illustrates the basic supply-bypassing
configuration and AGND/DGND connection for the
AD5547/AD5557.
V
DD
0.1碌F
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and V
DD
, as shown in Figure 20. As
a result, the voltage level of the logic input should not be greater
than the supply voltage.
V
DD
DIGITAL
INPUTS
5k鈩?/div>
DGND
Figure 20. Equivalent ESD Protection Circuits
Amplifier Selection
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. A 30 nA input
bias current in the op amp contributes to 1 LSB in the AD5547鈥檚
full-scale error. The OP1177 and AD8628 op amps are good
candidates for the I-V conversion.
03810-0-020
Reference Selection
The initial accuracy and rated output of the voltage reference
determine the full-span adjustment. The initial accuracy of the
reference is usually a secondary concern because it can be
trimmed. Figure 26 shows an example of a trimming circuit.
The zero-scale error can also be minimized by standard op amp
nulling techniques.
+ C2
5V
鈥?/div>
C1
1碌F
AD5547/AD5557
AGND
DGND
Figure 21. Power Supply Bypassing
Rev. 0 | Page 13 of 20
04452-0-015

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AD5557

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