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AD5932 Datasheet

  • AD5932

  • Programmable Single-Scan Waveform Generator

  • 812.00KB

  • 17頁

  • AD

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AD5932
SETTING UP THE FREQUENCY SCAN
As stated in the Frequency Profile section, the AD5932 requires
certain registers to be programmed to enable a frequency scan.
The Setting Up the Frequency Scan section discusses these
registers in more detail.
Number of Increments (N
INCR
)
An end frequency is not required on the AD5932. Instead, this
end frequency is calculated by multiplying the frequency
increment value (螖f) by the number of frequency steps (N
INCR
)
and adding it to/subtracting it from the start frequency (F
START
);
that is, F
START
+ N
INCR
脳 螖 f. The N
INCR
register is a 12-bit register,
with the address shown in the following bit map.
D15
0
D14
0
D13
0
D12
1
D11
12 bits of N
INCR
D0
<11鈥?>
Start Frequency (F
START
)
To start a frequency scan, the user needs to tell the AD5932
what frequency to start scanning from. This frequency is stored
in a 24-bit register called F
START
. If the user wishes to alter the
entire contents of the F
START
register, two consecutive writes
must be performed: one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, Control Bit B24
(D11) should be set to 1, with the LSBs programmed first.
In some applications, the user does not need to alter all 24 bits
of the F
START
register. By setting Control Bit B24 (D11) to 0, the
24-bit register operates as two 12-bit registers, one containing
the 12 MSBs and the other containing the 12 LSBs. This means
that the 12 MSBs of the F
START
word can be altered independently
of the 12 LSBs and vice versa. The addresses of both the LSBs
and the MSBs of this register are shown in the following bit map.
D15
1
1
D14
1
1
D13
0
0
D12
0
1
D11 to D0
12 LSBs of F
START
<11鈥?>
12 MSBs of F
START
<23鈥?2>
The number of increments is programmed in binary fashion,
with 000000000010 representing the minimum number of
frequency increments (two increments) and 111111111111
representing the maximum number of increments (4095).
Table 8. N
INCR
Data Bits
D11
0000
鈥?/div>
0000
D0
0010
Number of Increments
Two frequency increments. This is the
minimum number of frequency
increments.
Three frequency increments.
Four frequency increments.
鈥?/div>
4094 frequency increments.
4095 frequency increments.
0000
0000
鈥?/div>
1111
1111
0000
0000
鈥?/div>
1111
1111
0011
0100
鈥?/div>
1110
1111
Increment Interval (t
INT
)
The increment interval dictates the duration of the DAC output
signal for each individual frequency of the frequency scan. The
AD5932 offers the user two choices:
鈥?/div>
鈥?/div>
The duration is a multiple of cycles of the output frequency.
The duration is a multiple of MCLK periods.
Frequency Increments (螖f)
The value in the 螖f register sets the increment frequency for the
scan and is added incrementally to the current output frequency.
Note that the increment frequency can be positive or negative,
thereby giving an increasing or decreasing frequency scan.
At the start of a scan, the frequency contained in the F
START
register is output. Next, the frequency (F
START
+ 螖f ) is output.
This is followed by (F
START
+ 螖f + 螖f), and so on. Multiplying
the 螖f value by the number of increments (N
INCR
) and adding it
to the start frequency (F
START
) give the final frequency in the
scan. Mathematically, this final frequency/stop frequency is
represented by
F
START
+ (N
INCR
脳 螖f)
The 螖f register is a 23-bit register that requires two 16-bit writes
to be programmed. Table 7 gives the addresses associated with
both the MSB and LSB registers of the 螖f word.
Table 7. 螖f Register Bits
D15
0
0
0
D14
0
0
0
D13
1
1
1
D12
0
1
1
D11 D10 to D0
12 LSBs of
螖f
<11鈥?>
0
11 MSBs of
螖f
<22鈥?2>
1
11 MSBs of
螖f
<22鈥?2>
Scan
Direction
N/A
Positive
螖f
(F
START
+
螖f
)
Negative
螖f
(F
START
鈭?/div>
螖f
)
The desired choice is selected by Bit D13 in the t
INT
register as
shown in the following bit map.
D15
0
D14
1
D13
0
D12
x
D11
x
D10 to D0
11 bits <10鈥?>
Fixed number of output
waveform cycles.
11 bits <10鈥?>
Fixed number of clock
periods.
0
1
1
x
x
Programming of this register is in binary form, with the
minimum number being decimal 2. Note that 11 bits, D10 to
D0, of the register are available to program the time interval. As
an example, if MCLK = 50 MHz, then each clock period/base
interval is (1/50 MHz) = 20 ns. If each frequency must be output
for 100 ns, then <00000000101> or decimal 5 must be pro-
grammed to this register. Note that the AD5930 can output each
frequency for a maximum duration of 211 鈭?1 (or 2047) times
the increment interval.
Rev. 0 | Page 17 of 28

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