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AD7142 Datasheet

  • AD7142

  • Programmable Capacitance-to-Digital Converter with Environme...

  • 66頁

  • AD

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AD7142
START
AD7142-1 DEVICE ADDRESS
SDA
DEV
A6
DEV
A5
DEV
A4
DEV
A3
DEV DEV
A2
A1
DEV
A0
R/W ACK
REGISTER ADDRESS[A15:A8]
A15
A14
A9
A8
ACK
A7
REGISTER ADDRESS[A7:A0]
A6
A1
A0
ACK
t
1
SCLK
1
2
3
4
5
6
t
3
7
8
9
10
11
16
17
18
19
20
25
26
27
t
2
P
SR
DEV
A6
USING
REPEATED START
28
29
30
34
AD7142-1 DEVICE ADDRESS
DEV
A5
DEV
A1
DEV
A0
R/W
ACK
D7
REGISTER DATA[D7:D0]
D6
D1
D0
ACK
t
8
AD7142 DEVICE ADDRESS
DEV
A6
DEV
A5
DEV
A4
t
4
35
36
37
38
t
5
39
44
45
46
t
6
t
7
1
2
3
P
S
DEV
A6
AD7142-1 DEVICE ADDRESS
DEV
A5
DEV
A1
DEV
A0
R/W
ACK
D7
REGISTER DATA[D7:D0]
D6
D1
D0
ACK
P
SEPARATE READ AND
WRITE TRANSACTIONS
28
29
30
34
t
4
35
36
37
38
t
5
39
44
45
46
Figure 49. Example of I
2
C Timing for Single Register Readback Operation
WRITE
S
6-BIT DEVICE
ADDRESS W
REGISTER ADDR
[15:8]
REGISTER ADDR
[7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
ACK
ACK
ACK
ACK
ACK
ACK
P
READ (USING REPEATED START)
S
6-BIT DEVICE
ADDRESS W
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
ACK
ACK
ACK
SR
R
ACK
ACK
ACK
ACK P
READ (WRITE TRANSACITON SETS UP REGISTER ADDRESS)
R
ACK
ACK
S
P
ACK
6-BIT DEVICE
ADDRESS W
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
S 6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
ACK
ACK
ACK
ACK P
05702-039
OUTPUT FROM MASTER
OUTPUT FROM AD7142
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT
ACK = NO ACKNOWLEDGE BIT
Figure 50. Example of Sequential I
2
C Write and Readback Operation
V
DRIVE
INPUT
The supply voltage to all pins associated with both the I
2
C and
SPI serial interfaces (SDO, SDI, SCLK, SDA, and CS) is separate
from the main V
CC
supplies and is connected to the V
DRIVE
pin.
This allows the AD7142 to be connected directly to processors
whose supply voltage is less than the minimum operating
voltage of the AD7142 without the need for external level-
shifters. The V
DRIVE
pin can be connected to voltage supplies as
low as 1.65 V and as high as DV
CC
.
Rev. 0 | Page 34 of 68
05702-038
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARE BITS.
5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB X鈥檚 ARE DON鈥橳 CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.

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