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AD7142 Datasheet

  • AD7142

  • Programmable Capacitance-to-Digital Converter with Environme...

  • 3076.70KB

  • 66頁

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AD7142
GPIO INT OUTPUT CONTROL
The INT output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt
configuration register to 01. See the GPIO section for more
information on how to configure the GPIO.
Enable the GPIO interrupt by setting the GPIO_INT_EN bit in
Register 0x007 to 1, or disable the GPIO interrupt by clearing this
bit to 0. The GPIO status bit in the conversion complete interrupt
status register reflects the status of the GPIO interrupt. This bit is
set to 1 when the GPIO has triggered INT. The bit is cleared on
readback from the register, provided the condition that caused
the interrupt has gone away.
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 14
shows how the settings of the GPIO_INPUT_CONFIG bits in
the interrupt enable register affect the behavior of INT.
Figure 38 to Figure 41 show how the interrupt output is cleared
on a read from the CDC conversion complete interrupt status
register.
1
SERIAL
READBACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
INPUT
SERIAL
READBACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
INPUT
INT
OUTPUT
1
INT
OUTPUT
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
05702-028
Figure 38. INT Output Controlled by the GPIO Input Example,
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00
Figure 39. INT Output Controlled by the GPIO Input Example,
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01
Rev. 0 | Page 27 of 68
05702-029
NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.
NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.

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