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CS5341 Datasheet

  • CS5341

  • 105 dB, 192 kHz, MULTI-BIT AUDIO A/D CONVERTER

  • 25頁(yè)

  • CIRRUS

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CS5341
4.2.3
Master Clock
The CS5341 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is
also an internal MCLK divider which is automatically activated based on the speed mode and frequency of the
MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. Table 4 lists some common au-
dio output sample rates and the required MCLK frequency. Please note that not all of the listed sample rates are
supported when operating with a fast MCLK (512x, 256x, 128x for Single, Double, and Quad Speed Modes respec-
tively).
Single Speed Mode
MCLK/LRCK Ratio
256x, 512x
* Quad Speed, 64x only available in Master Mode.
Table 3. Master Clock (MCLK) Ratios
Double Speed Mode
128x, 256x
Quad Speed Mode
64x*,128x
SAMPLE RATE (kHz)
32
44.1
48
64
88.2
96
192
MCLK (MHz)
8.192
11.2896
22.5792
12.288
24.576
8.192
11.2896
22.5792
12.288
24.576
12.288
24.576
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3
Serial Audio Interface
The CS5341 supports both I
2
S and Left Justified serial audio formats. Upon start-up, the CS5341 will detect the logic
level on SDOUT (pin 4). A 10 k
鈩?/div>
pull-up to VL is needed to select I
2
S format, and a 10 k
鈩?/div>
pull-down to GND is
needed to select Left Justified format. Please see Figures 13 through 16 on page 14, for more information on the
required timing for the two serial audio interface formats.
LR C K
Le ft C hann el
R ig ht C ha nnel
S C LK
SD A TA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 19. Left-Justified Serial Audio Interface
LRCK
Le ft C h an n e l
R ig h t C h a nn el
S C LK
SDA TA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 2 2
Figure 20. I
2
S Serial Audio Interface
DS564PP2
19

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