CS5341
4 APPLICATIONS
4.1
Single, Double, and Quad Speed Modes
The CS5341 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined
by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
MCLK/LRCK
Ratio
512x
256x
256x
128x
128x
64x*
* Quad Speed Mode, 64x only available in Master Mode.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
Speed Mode
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Output Sample Rate Range (kHz)
43 - 54
2 - 54
86 - 108
50 - 108
172 - 200
100 - 200
4.2
Operation as Either a Clock Master or Slave
The CS5341 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are
outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK
pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master
or slave is made via the Mode pins as shown in Table 2.
M1 (Pin 16)
0
0
1
1
M0 (Pin 1)
0
1
0
1
MODE
Clock Master, Single Speed Mode
Clock Master, Double Speed Mode
Clock Master, Quad Speed Mode
Clock Slave, All Speed Modes
Table 2. CS5341 Mode Control
DS564PP2
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