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CS8416 Datasheet

  • CS8416

  • 192 kHz Digital Audio Interface Receiver

  • 63頁(yè)

  • CIRRUS

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CS8416
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(T
A
= 25 擄C for suffixes 鈥楥S鈥?& 鈥機(jī)Z鈥? T
A
= -40 to 85 擄C for 鈥業(yè)S鈥?& 鈥業(yè)Z鈥?; VA+ = VD+ = 3.3 V 鹵 5%, VL+ = 3.135 V to 5.5
V, Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
L
= 20 pF)
Parameter
OSCLK Active Edge to SDOUT Output Valid
Master Mode
RMCK to OSCLK active edge delay
RMCK to OLRCK delay
OSCLK and OLRCK Duty Cycle
Slave Mode
OSCLK Period
OSCLK Input Low Width
OSCLK Input High Width
OSCLK Active Edge to OLRCK Edge
OSCLK Edge Setup Before OSCLK Active-Edge
(Notes
5,6,7)
(Notes
5,6,8)
t
sckw
t
sckl
t
sckh
t
lrckd
t
lrcks
36
14
14
10
10
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
(Note
5)
(Note
6)
t
smd
t
lmd
0
0
-
-
-
50
10
10
-
ns
ns
%
(Note 5)
Symbol
t
dpd
Min
-
Typ
-
Max
15
Units
ns
Notes: 5. In Software mode the active edges of OSCLK are programmable.
6. In Software mode the polarity of OLRCK is programmable.
7. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
8. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
O S CLK
(o u tp u t)
OLRCK
(input)
t lrckd
t lrcks
t sckh
t sckl
OLR CK
(o u tp u t)
t sm d
t
RMCK
(o utp ut)
lm d
OSCLK
(input)
t sckw
t dpd
SDOUT
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
DS578PP2
7

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