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CS8406 Datasheet

  • CS8406

  • 192 kHz Digital Audio Interface Transmitter

  • 40頁

  • CIRRUS

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CS8406
If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically
calculated by the CS8406, and does not have to be written into the last byte of the block by the
host microcontroller. This is also true if the channel status data is entered serially through the
COPY/C pin when the part is in hardware mode.
E to F interrupt occurs
Optionally set E to F inhibit
Write E data
If set, clear E to F inhibit
Wait for E to F transfer
Return
Figure 17. Flowchart for Writing the E Buffer
15.1.2 Serial Copy Management System
(SCMS)
In software mode, the CS8406 allows read/modify/write access to all the channel status bits. For
consumer mode SCMS compliance, the host microcontroller needs to manipulate the Category
Code, Copy bit and L bit appropriately.
In hardware mode, the SCMS protocol can be followed by either using the COPY and ORIG input
pins, or by using the C bit serial input pin. These options are documented in the hardware mode
section of this data sheet.
15.1.3 Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data,
and the LS Byte is the B channel data (see Figure 16).
There are two methods of accessing this memory, known as one byte mode and two byte mode.
The desired mode is selected through a control register bit.
15.1.3.1 One Byte mode
In many applications, the channel status blocks for the A and B channels will be identical. In this
situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the
other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would
be necessary to write the same byte to the other block. One byte mode takes advantage of the
often identical nature of A and B channel status data.
When reading data in one byte mode, a single byte is returned, which can be from channel A or
B data, depending on a register control bit. If a write is being done, the CS8406 expects a single
DS580F1
41

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