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CS8406 Datasheet

  • CS8406

  • 192 kHz Digital Audio Interface Transmitter

  • 904.00KB

  • 40頁

  • CIRRUS

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CS8406
TCBL
(In/Output)
VLRCK
V/C/U
(Input)
Tth
Tsetup
VCU[0]
Thold
VCU[1]
VCU[2]
VCU[3]
VCU[4]
SDIN
(Input)
TXP(N)
(Output)
Z
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
Data [0]
Y
Data [1]
X
Data [2]
Y
Data [3]
X
Data [4]
AES3 Transmitter in Stereo mode
Tsetup
鈮?/div>
7.5% AES3 frame time
Thold = 0
Tth > 3 OMCK clocks, if TCBL is Input
TCBL
(In/Output)
VLRCK
Tth
U
(Input)
SDIN
(Input)
TXP(N)
(Output)
Z
Data [4]
Data [5]
U[0]
U[2]
Data [6]
Data [7]
Data [8]
Data [0]*
Y
Data [2]*
X
Data [4]*
* Assume MMTLR = 0
TXP(N)
(Output)
Z
Data [1]*
Y
Data [3]*
X
Data [5]*
* Assume MMTLR = 1
Tsetup
鈮?/div>
15% AES3 frame time
Thold = 0
Tth > 3 OMCK clocks, if TCBL is Input
AES3 Transmitter in Mono mode
鈥LRCK
is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.
鈥LRCK
duty cycle is 50%.
鈥n
stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, VLRCK frequency = 2xAES3 frame rate.
鈥f
the serial audio input port is on slave mode and TCBL is an output, then VLRCK = ILRCK if SILRPOL = 0
and VLRCK = ILRCK if SILRPOL =1.
鈥f
the serial audio input port is in master mode and TCBL is an input, then VLRCK = ILRCK if SILRPOL = 0
and VLRCK = ILRCK if SILRPOL =1.
Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data
18
DS580F1

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