CS8406
Left
ILRCK
Left
ISCLK
Justified
SDIN
(In)
Right
MSB
LSB
MSB
LSB
MSB
I S
(In)
2
ILRCK
ISCLK
SDIN
Left
Right
MSB
LSB
MSB
LSB
MSB
ILRCK
Right
ISCLK
Justified
(In)
SDIN
Left
Right
LSB
MSB
LSB
MSB
LSB
SIMS*
SISF*
SIRES[1:0]*
SIJUST*
SIDEL*
SISPOL*
SILRPOL*
Left Justified
I虜S
Right Justified
X
X
X
X
X
X
00+
00+
XX
0
0
1
0
1
0
0
0
0
0
1
0
X = don鈥檛 care to match format, but does need to be set to the desired setting
+ I虜S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
* See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 7. Serial Audio Input Example Formats
DS580F1
15