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CY7C1305AV25-133BZC Datasheet

  • CY7C1305AV25-133BZC

  • 18-Mbit Burst of 4 Pipelined SRAM with QDR? Architecture

  • 804.00KB

  • 22頁

  • CYPRESS

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PRELIMINARY
Write Cycle Descriptions
(CY7C1307AV25)
[2, 10]
BWS
0
L
L
L
BWS
1
L
L
H
BWS
2
L
L
H
BWS
3
L
L
H
K
L-H
鈥?/div>
L-H
K
鈥?/div>
L-H
鈥?/div>
CY7C1305AV25
CY7C1307AV25
Comments
During the Data portion of a Write sequence, all four bytes
(D
[35:0]
) are written into the device.
During the Data portion of a Write sequence, all four bytes
(D
[35:0]
) are written into the device.
During the Data portion of a Write sequence, only the lower
byte (D
[8:0]
) is written into the device. D
[35:9]
will remain un-
altered.
During the Data portion of a Write sequence, only the lower
byte (D
[8:0]
) is written into the device. D
[35:9]
will remain un-
altered.
During the Data portion of a Write sequence, only the byte
(D
[17:9]
) is written into the device. D
[8:0]
and D
[35:18]
will re-
main unaltered.
During the Data portion of a Write sequence, only the byte
(D
[17:9]
) is written into the device. D
[8:0]
and D
[35:18]
will re-
main unaltered.
During the Data portion of a Write sequence, only the byte
(D
[26:18]
) is written into the device. D
[17:0]
and D
[35:27]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[26:18]
) is written into the device. D
[17:0]
and D
[35:27]
will
remain unaltered.
During the Data portion of a Write sequence, only the byte
(D
[35:27]
) is written into the device. D
[26:0]
will remain unal-
tered.
L
H
H
H
鈥?/div>
L-H
H
L
H
H
L-H
鈥?/div>
H
L
H
H
鈥?/div>
L-H
H
H
L
H
L-H
鈥?/div>
H
H
L
H
鈥?/div>
L-H
H
H
H
L
L-H
H
H
H
L
鈥?/div>
L-H
During the Data portion of a Write sequence, only the byte
(D
[35:27]
) is written into the device. D
[26:0]
will remain unal-
tered.
No data is written into the device during this portion of a Write
operation.
No data is written into the device during this portion of a write
operation.
H
H
H
H
H
H
H
H
L-H
鈥?/div>
鈥?/div>
L-H
Note:
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
0
and BWS
1
in the case of CY7C1305AV25 and BWS
2
and BWS
3
in
the case of CY7C1307AV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05496 Rev. *A
Page 8 of 21

CY7C1305AV25-133BZC PDF文件相關(guān)型號

CY7C1305AV25-167BZC,CY7C1307AV25-100BZC,CY7C1307AV25-133BZC

CY7C1305AV25-133BZC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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