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CY7C1460AV33 Datasheet

  • CY7C1460AV33

  • 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL...

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  • CYPRESS

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PRELIMINARY
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan Order-165FBGA
Boundary Scan Order- 209BGA
Bit Size (脳36)
3
1
32
89
-
Bit Size (脳18)
3
1
32
89
-
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Bit Size (脳72)
3
1
32
-
138
Identification Codes
Instruction
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Code
000
001
010
011
100
101
110
111
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05353 Rev. *A
Page 15 of 27

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