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ISL6560CB Datasheet

  • ISL6560CB

  • Microprocessor CORE Voltage Regulator Two-Phase Buck PWM Con...

  • 14頁

  • INTERSIL   INTERSIL

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ISL6560
MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the following
equations). The conduction losses are the main component
of power dissipation for the lower MOSFETs, Q2 and Q4 of
Figure 10. Only the upper MOSFETs, Q1 and Q3 have
significant switching losses, since the lower device turns on
and off into near-zero voltage.
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET鈥檚 body diode. The gate-charge losses are
dissipated by the driver IC and don't heat the MOSFETs.
However, large gate-charge increases the switching time,
t
SW
which increases the upper MOSFET switching losses.
L3
12V
+V
IN
1碌H
2 - 4.7碌F
C41-42
10鈩?/div>
R6
4.7碌F
C40
1 VID4
INPUT
VID CODES
from
PROCSSOR {
{
22k
R11
1nF C12
15k
R12
4.3k
R27
1k
R5
2 VID3
3 VID2
4 VID1
5 VID0
6 COMP
7 FB
8 CT
VCC 16
REF 15
CS- 14
PWM1 13
PWM2 12
CS+ 11
PWRGD 10
GND 9
1nF
C10
330pF
C11
5m鈩?/div>
R13
20鈩?/div>
R14
15nF
C20
R7
330鈩?/div>
0.1碌F
1 UGATE PHASE 8
2 BOOT
3 PWM
4 GND
PVCC 7
900nH
VCC 6
LGATE 5
1碌F
C2
C21, C24-28
6 - 1200碌F
+V
CORE
Q2 HUF76145
C1
L1
Q1 HUF76139
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. A separate heat sink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
I
O
脳
r
DS
(
ON
)
脳
V
OUT
I
O
脳
V
IN
脳
t
SW
脳
F
S
P
UPPER
= ----------------------------------------------------------- + ----------------------------------------------------
-
V
IN
2
I
O
脳
r
DS
(
ON
)
脳 (
V
IN
鈥?/div>
V
OUT
)
-
P
LOWER
= --------------------------------------------------------------------------------
V
IN
2
2
Figure 10 shows a schematic of the circuit developed from
the proceeding computations. This circuit is implemented on
the ISL6560/62 Evaluation Board. The next section will
discuss PC board layout.
6 - 470碌F
C15, C17-18, C29, C50-51
HIP6601ECB
150pF ISL6560
C14
100pF
C13
0.1碌F
1 UGATE PHASE 8
2 BOOT
3 PWM
4 GND
PVCC 7
VCC 6
LGATE 5
1碌F
C4
C3
Q3
HUF76139
L2
900nH
Q4
HUF76145
16 - 22碌F
C19, C30,
C34-37,
C39, C45-49,
C60-63
HIP6601ECB
FIGURE 10. SCHEMATIC DIAGRAM OF A 40A SUPPLY USING THE ISL6560 CONTROLLER AND HIP6601 GATE DRIVERS
PC Board Layout Considerations
Like all high-current supplies where low-voltage control
signals in the millivolt range must live with high voltage and
high-current switching signals, PC board layout becomes
crucial in obtaining a satisfactory supply.
Figure 11 shows a simplified diagram of the critical areas of
a PC board layout. This diagram and the following material
represent goals to work towards during the layout phase.
Goals will be compromised during the layout process due to
11
component placement and space constraints. The following
text reviews these layout considerations in more detail.
Current Sampling
1. Place the current sampling or sense resistor as close as
possible to the upper MOSFET drains. This is important
since the added inductance and resistance increase the
impedance and result in a reduction in drain voltage
during high peak pulse currents.
FN9011.3

ISL6560CB 產(chǎn)品屬性

  • 48

  • 集成電路 (IC)

  • PMIC - 穩(wěn)壓器 - DC DC 切換控制器

  • -

  • 電流模式

  • 1

  • 2MHz

  • 50%

  • 3 V ~ 12 V

  • 是

  • 無

  • 無

  • 無

  • 無

  • 無

  • 無

  • 無

  • 0°C ~ 70°C

  • 16-SOIC（0.154"，3.90mm 寬）

  • 管件

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