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IS42S16160B Datasheet

  • IS42S16160B

  • 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

  • 62頁

  • ISSI   ISSI

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IS42S83200B,
IS42S16160B
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing (CAS latency) later.
The PRECHARGE to bank n will begin after t
DPL
is met,
where t
DPL
begins when the READ to bank m is registered.
The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
4. Interrupted by a WRITE (with or without auto precharge):
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
t
DPL
is met, where t
DPL
begins when the WRITE to bank m
is registered. The last valid data WRITE to bank n will be
data registered one clock prior to a WRITE to bank m.
WRITE With Auto Precharge interrupted by a READ
T0
CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
NOP
WRITE - AP
BANK n
NOP
READ - AP
BANK m
NOP
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
t
DPL
- BANK n
Precharge
t
RP - BANK n
t
RP - BANK m
Precharge
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS
BANK n,
COL a
BANK m,
COL b
DQ
D
IN
a
D
IN
a+1
CAS Latency - 3 (BANK m)
D
OUT
b
D
OUT
b+1
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
NOP
WRITE - AP
BANK n
NOP
NOP
WRITE - AP
BANK m
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
t
DPL
- BANK n
Precharge
t
RP - BANK n
t
DPL - BANK m
Write-Back
Internal States
BANK m
Page Active
WRITE with Burst of 4
ADDRESS
BANK n,
COL a
BANK m,
COL b
DQ
D
IN
a
D
IN
a+1
D
IN
a+2
D
IN
b
D
IN
b+1
D
IN
b+2
D
IN
b+3
DON'T CARE
50
Integrated Silicon Solution, Inc. 鈥?www.issi.com
Rev. C
03/13/07

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