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IS42S16160B Datasheet

  • IS42S16160B

  • 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

  • 62頁(yè)

  • ISSI   ISSI

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IS42S83200B,
CHIP OPERATION
IS42S16160B
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a
bank within the SDRAM, a row in that bank must be 鈥渙pened.鈥?/div>
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see
Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the t
RCD
specification. Minimum t
RCD
should be
divided by the clock period and rounded up to the next whole
number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command
can be entered. For example, a t
RCD
specification of 15ns
with a 143 MHz clock (7ns period) results in 2.14 clocks,
rounded to 3. This is reflected in the following example,
which covers any case where 2 < [t
RCD
(MIN)/t
CK
]
鈮?/div>
3. (The
same procedure is used to convert other specification limits
from time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row
has been 鈥渃losed鈥?(precharged). The minimum time interval
between successive ACTIVE commands to the same bank
is defined by t
RC
.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by t
RRD
.
CLK
HIGH
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
ROW ADDRESS
BANK ADDRESS
EXAMPLE: MEETING TRCD (MIN) WHEN 2
<
[TRCD (MIN)/TCK]
鈮?/div>
3
T0
CLK
T1
T2
T3
T4
COMMAND
ACTIVE
NOP
t
RCD
NOP
READ or
WRITE
DON'T CARE
Integrated Silicon Solution, Inc. 鈥?www.issi.com
Rev. C
03/13/07
27

IS42S16160B相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
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  • 英文版
    OPTICALLY COUPLED BILATERAL SWITCH LIGHT ACTIVATED ZERO VOLT...
    ETC [ETC]
  • 英文版
    OPTICALLY COUPLED BILATERAL SWITCH LIGHT ACTIVATED ZERO VOLT...
    ETC [ETC]
  • 英文版
    OPTICALLY COUPLED BILATERAL SWITCH LIGHT ACTIVATED ZERO VOLT...
    ETC [ETC]
  • 英文版
    OPTICALLY COUPLED BILATERAL SWITCH LIGHT ACTIVATED ZERO VOLT...
    ETC [ETC]
  • 英文版
    2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dyn...
    ICSI [Inte...
  • 英文版
    256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
    ISSI
  • 英文版
    256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
    ISSI [Inte...
  • 英文版
    512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC...
    ISSI [Inte...
  • 英文版
    128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI
  • 英文版
    128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI [Inte...
  • 英文版
    2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dyn...
    ICSI [Inte...
  • 英文版
    512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI
  • 英文版
    512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI [Inte...
  • 英文版
    2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dyn...
    ICSI [Inte...
  • 英文版
    256 Mb Synchronous DRAM
    ISSI
  • 英文版
    32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM
    ISSI
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ISSI
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ISSI [Inte...
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ETC
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ETC [ETC]

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