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IS42S16160B Datasheet

  • IS42S16160B

  • 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

  • 62頁(yè)

  • ISSI   ISSI

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IS42S83200B,
IS42S16160B
CKE RELATED COMMAND TRUTH TABLE
(1)
CKE
Current State
Self-Refresh (S.R.)
Operation
INVALID, CLK (n - 1) would exit S.R.
Self-Refresh Recovery
(2)
Self-Refresh Recovery
(2)
Illegal
Illegal
Maintain S.R.
Idle After t
RC
Idle After t
RC
Illegal
Illegal
Begin clock suspend next cycle
(5)
Begin clock suspend next cycle
(5)
Illegal
Illegal
Exit clock suspend next cycle
(2)
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
EXIT P.D. --> Idle
(2)
Maintain power down mode
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Auto-Refresh
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Self-Refresh
(3)
Refer to operations in Operative Command Table
Power-Down
(3)
Refer to operations in Operative Command Table
Begin clock suspend next cycle
(4)
Exit clock suspend next cycle
Maintain clock suspend
n-1
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
n
X
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
X
H
L
H
H
H
H
H
L
L
L
L
L
X
H
L
H
L
CS
X
H
L
L
L
X
H
L
L
L
H
L
L
L
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
RAS
X
X
H
H
L
X
X
H
H
L
X
H
H
L
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
CAS
X
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
WE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
Address
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
鈥?/div>
X
X
鈥?/div>
鈥?/div>
鈥?/div>
X
Op - Code
鈥?/div>
鈥?/div>
鈥?/div>
X
Op - Code
X
X
X
X
X
Self-Refresh Recovery
Power-Down(P.D.)
All Banks Idle
Any state
other than
listed above
Notes:
1. H : High level, L : low level, X : High or low level (Don鈥檛 care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if t
XSR
is not satisfied.
Integrated Silicon Solution, Inc. 鈥?www.issi.com
Rev. C
03/13/07
13

IS42S16160B相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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  • 英文版
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    ETC [ETC]
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    OPTICALLY COUPLED BILATERAL SWITCH LIGHT ACTIVATED ZERO VOLT...
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    OPTICALLY COUPLED BILATERAL SWITCH LIGHT ACTIVATED ZERO VOLT...
    ETC [ETC]
  • 英文版
    2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dyn...
    ICSI [Inte...
  • 英文版
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    ISSI
  • 英文版
    256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
    ISSI [Inte...
  • 英文版
    512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC...
    ISSI [Inte...
  • 英文版
    128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI
  • 英文版
    128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI [Inte...
  • 英文版
    2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dyn...
    ICSI [Inte...
  • 英文版
    512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI
  • 英文版
    512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC ...
    ISSI [Inte...
  • 英文版
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    ICSI [Inte...
  • 英文版
    256 Mb Synchronous DRAM
    ISSI
  • 英文版
    32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM
    ISSI
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ISSI
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ISSI [Inte...
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ETC
  • 英文版
    1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...
    ETC [ETC]

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