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IS42S16160B Datasheet

  • IS42S16160B

  • 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

  • 62頁

  • ISSI   ISSI

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IS42S83200B,
CS
H
L
L
L
L
L
L
L
L
Write Recovering
with Auto
Precharge
H
L
L
L
L
L
L
L
L
Refresh
H
L
L
L
L
L
L
L
Mode Register
Accessing
H
L
L
L
L
IS42S16160B
RAS CAS
脳
H
H
H
H
L
L
L
L
脳
H
H
H
H
L
L
L
L
脳
H
H
H
L
L
L
L
脳
H
H
H
L
脳
H
H
L
L
H
H
L
L
脳
H
H
L
L
H
H
L
L
脳
H
L
L
H
H
L
L
脳
H
H
L
脳
WE
脳
H
L
H
L
H
L
H
L
脳
H
L
H
L
H
L
H
L
脳
脳
H
L
H
L
H
L
脳
H
L
脳
脳
FUNCTIONAL TRUTH TABLE Continued:
Current State
Write Recovering
Address
脳
脳
脳
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
脳
OC, BA
脳
脳
脳
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
脳
OC, BA
脳
脳
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
脳
OC, BA
脳
脳
脳
BA, CA, A10
BA, RA
Command
DESL
NOP
BST
READ/READA
WRIT/ WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL
REF/MRS
Action
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Begin read
(8)
Begin new write
ILLEGAL
(3)
ILLEGAL
(3)
ILLEGAL
ILLEGAL
Nop, Enter precharge after tDPL
Nop, Enter precharge after tDPL
Nop, Enter row active after tDPL
ILLEGAL
(3,8,11)
ILLEGAL
(3,11)
ILLEGAL
(3,11)
ILLEGAL
(3,11)
ILLEGAL
ILLEGAL
Nop, Enter idle after tRC
Nop, Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter idle after 2 clocks
Nop, Enter idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL
Note: H=V
IH
, L=V
IL
x= V
IH
or V
IL
, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don鈥檛 satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
12
Integrated Silicon Solution, Inc. 鈥?www.issi.com
Rev. C
03/13/07

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