bq4013/Y/LY
www.ti.com
SLUS121A 鈥?MAY 1999 鈥?REVISED MAY 2007
When V
CC
falls below the V
PFD
threshold, the SRAM automatically write-protects the data. All outputs become
high impedance, and all inputs are treated as
don't care.
If a valid access is in process at the time of power-fail
detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time t
WPT
,
write-protection takes place.
As V
CC
falls past V
PFD
and approaches V
SO
, the control circuitry switches to the internal lithium backup supply,
which provides data retention until valid V
CC
is applied.
When V
CC
returns to a level above the internal backup cell voltage, the supply is switched back to V
CC
. After V
CC
ramps above the V
PFD
threshold, write-protection continues for a time t
CER
(120 ms maximum in 5-V system, 85
ms maximum in 3.3-V system) to allow for processor stabilization. Normal memory operation may resume after
this time.
The internal coin cells used by the bq4013/Y/LY have an extremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
As shipped from TI, the integral lithium cells of the MT-type module are electrically isolated from the memory.
(Self-discharge in this condition is approximately 0.5% per year.) Following the first application of V
CC
, this
isolation is broken, and the lithium backup provides data retention on subsequent power-downs.
BLOCK DIAGRAM
DIP MODULE
bq4013/Y/LY
MA PACKAGE
OE
128 k 脳 8
SRAM
Block
A
0
- A
16
DQ
0
- DQ
7
WE
Power
CE
CON
CE
Power-Fail
Control
V
CC
+
Lithium
Cell
UDG-06075
TRUTH TABLE
MODE
Not selected
Output disable
Read
Write
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
I/O OPERATION
High-Z
High-Z
D
OUT
D
IN
POWER
Standby
Active
Active
Active
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