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TMS320C2801 Datasheet

  • TMS320C2801

  • TMS320F2809, F2808, F2806, F2802, F2801, C2802, C2801, UCD95...

  • 134頁

  • TI

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230H 鈥?OCTOBER 2003 鈥?REVISED JUNE 2006
www.ti.com
eCAN-B Control and Status Registers
Mailbox Enable 鈭?CANME
Mailbox Direction 鈭?CANMD
Transmission Request Set 鈭?CANTRS
Transmission Request Reset 鈭?CANTRR
Transmission Acknowledge 鈭?CANTA
eCAN-B Memory (512 Bytes)
6200h
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Local Acceptance Masks (LAM)
(32
脳
32-Bit RAM)
Message Object Time Stamps (MOTS)
(32
脳
32-Bit RAM)
Message Object Time-Out (MOTO)
(32
脳
32-Bit RAM)
Control and Status Registers
Abort Acknowledge 鈭?CANAA
Received Message Pending 鈭?CANRMP
Received Message Lost 鈭?CANRML
Remote Frame Pending 鈭?CANRFP
Global Acceptance Mask 鈭?CANGAM
Master Control 鈭?CANMC
Bit-Timing Configuration 鈭?CANBTC
Error and Status 鈭?CANES
Transmit Error Counter 鈭?CANTEC
Receive Error Counter 鈭?CANREC
Global Interrupt Flag 0 鈭?CANGIF0
Global Interrupt Mask 鈭?CANGIM
eCAN-B Memory RAM (512 Bytes)
6300h鈭?307h
6308h鈭?30Fh
6310h鈭?317h
6318h鈭?31Fh
6320h鈭?327h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Global Interrupt Flag 1 鈭?CANGIF1
Mailbox Interrupt Mask 鈭?CANMIM
Mailbox Interrupt Level 鈭?CANMIL
Overwrite Protection Control 鈭?CANOPC
TX I/O Control 鈭?CANTIOC
RX I/O Control 鈭?CANRIOC
Time Stamp Counter 鈭?CANTSC
Time-Out Control 鈭?CANTOC
Time-Out Status 鈭?CANTOS
63E0h鈭?3E7h
63E8h鈭?3EFh
63F0h鈭?3F7h
63F8h鈭?3FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Message Mailbox (16 Bytes)
63E8h鈭?3E9h
63EAh鈭?3EBh
63ECh鈭?3EDh
63EEh鈭?3EFh
Message Identifier 鈭?MSGID
Message Control 鈭?MSGCTRL
Message Data Low 鈭?MDL
Message Data High 鈭?MDH
Reserved
Figure 4-12. eCAN-B Memory Map
The CAN registers listed in
Table 4-7
are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
68
Peripherals

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