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TMS320C2801 Datasheet

  • TMS320C2801

  • TMS320F2809, F2808, F2806, F2802, F2801, C2802, C2801, UCD95...

  • 134頁(yè)

  • TI

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230H 鈥?OCTOBER 2003 鈥?REVISED JUNE 2006
XCLKIN
X1
X2
External Clock Signal
(Toggling 0 鈭扸
DDIO
)
NC
Figure 3-11. Using a 3.3-V External Oscillator
X2
XCLKIN
X1
External Clock Signal
(Toggling 0 鈭扸
DD
)
NC
Figure 3-12. Using a 1.8-V External Oscillator
XCLKIN
X1
X2
C
L1
Crystal
C
L2
Figure 3-13. Using the Internal Oscillator
3.6.1.1
External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
鈥?/div>
Fundamental mode, parallel resonant
鈥?/div>
C
L
(load capacitance) = 12 pF
鈥?/div>
C
L1
= C
L2
= 24 pF
鈥?/div>
C
shunt
= 6 pF
鈥?/div>
ESR range = 30 to 60
鈩?/div>
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
takes 131072 OSCCLK cycles.
Functional Overview
47

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