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TPS40007 Datasheet

  • TPS40007

  • 低輸入 (2.25V-5.5V) 300kHz 頻率的同步降壓控制器，具有輸出驅(qū)...

  • 634.57KB

  • 26頁

  • TI

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TPS40007
TPS40009
SLUS589A鈭?NOVEMBER 2003 鈭?REVISED MAY 2004
APPLICATION INFORMATION
ERROR AMPLIFIER
The error amplifier has a bandwidth of greater than 5 MHz, with open loop gain of at least 55 dB. The COMP
output voltage is clamped to a level above the oscillator ramp in order to improve large-scale transient response.
OSCILLATOR
The oscillator uses an internal resistor and capacitor to set the oscillation frequency. The ramp waveform is a
sawtooth at the PWM frequency with a peak voltage of 1.25 V, and a valley of 0.31 V. The PWM duty cycle is
limited to a maximum of 94%, allowing the bootstrap capacitor to charge during every cycle.
BOOTSTRAP/CHARGE PUMP
There is an internal switch between VDD and BOOT. This switch charges the external bootstrap capacitor for
the floating supply. If the resistance of this switch is too high for the application, an external schottky diode
between VDD and BOOT can be used. The peak voltage on the bootstrap capacitor is approximately equal to
VDD.
DRIVER
The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.5 V. At V
IN
, = 5 V
and using appropriate MOSFETs, a 20-A converter can be achieved. The LDRV driver switches between VDD
and ground, while the HDRV driver is referenced to SW and switches between BOOT and SW.
SYNCHRONOUS RECTIFICATION AND PREDICTIVE DELAY
In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This
current cannot be stopped immediately without using infinite voltage. In order to provide a path for current to
flow and maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a
conventional diode, or it can be a controlled active device if a control signal is available to drive it. The TPS4000x
provides a signal to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with
the drive signal for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns
off and the main switch turns on, and minimum delay from when the main switch turns off and the rectifier
MOSFET turns on. This scheme, Predictive Gate Drivet delay, uses information from the current switching
cycle to adjust the delays that are to be used in the next cycle. Figure 2 shows the switch-node voltage waveform
for a synchronously rectified buck converter. Illustrated are the relative effects of a fixed-delay drive scheme
(constant, pre-set delays for the turn-off to turn-on intervals), an adaptive delay drive scheme (variable delays
based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme.
Note that the longer the time spent in diode conduction during the rectifier conduction period, the lower the
efficiency. Also, not described in Figure 2 is the fact that the predictive delay circuit can prevent the body diode
from becoming forward biased at all. This results in a significant power savings when the main MOSFET turns
on, and minimizes reverse recovery loss in the body diode of the rectifier MOSFET.
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