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TPS40007 Datasheet

  • TPS40007

  • 低輸入 (2.25V-5.5V) 300kHz 頻率的同步降壓控制器，具有輸出驅(qū)...

  • 26頁(yè)

  • TI

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TPS40007
TPS40009
SLUS589A鈭?NOVEMBER 2003 鈭?REVISED MAY 2004
Terminal Functions
TERMINAL
NAME
BOOT
COMP
FB
GND
HDRV
NO.
10
3
2
5
9
I/O
O
O
I
鈭?/div>
O
DESCRIPTION
Provides a bootstrapped supply for the topside MOSFET driver, enabling the gate of the topside
MOSFET to be driven above the input supply rail
Output of the error amplifier
Inverting input of the error amplifier. In normal operation the voltage at this pin is the internal reference level of 700 mV.
Power supply return for the device. The power stage ground return on the board requires a separate path from other
sensitive signal ground returns.
This is the gate drive output for the topside N-channel MOSFET. HDRV is bootstrapped to near 2
脳
VDD for good en-
hancement of the topside MOSFET.
A resistor is connected between this pin and VDD to set up the over current threshold voltage. A 15-碌A(chǔ) current sink at
the pin establishes a voltage drop across the external resistor that represents the drain-to-source voltage across the
top side N-channel MOSFET during an over current condition. The ILIM over current comparator is blanked for the
first 100 ns to allow full enhancement of the top MOSFET. Set the ILIM voltage level such that it is within 800 mV of
VDD; that is, (VDD 鈭?0.8)
鈮?/div>
IILIM
鈮?/div>
VDD.
Gate drive output for the low-side synchronous rectifier N-channel MOSFET
Soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor connected to this pin.
A closed loop soft-start occurs when the internal 3-碌A(chǔ) current source charges the external capacitor. There is a 0.65-V
offset between external SS pin and internal soft-start voltage at the error amplifier input. This allows the device to be
enabled before starting VOUT, thus ensuring that VOUT soft starts smoothly. When the SS/SD voltage is less than 0.25
V, the device is shutdown and the HDRV and LDRV are driven low. In normal operation, the capacitor is charged to
VDD. When a fault condition is asserted, the soft-start capacitor goes through six charge/discharge cycles, restarting
the converter on the seventh cycle.
Connect to the switched node on the converter. This pin is used for overcurrent sensing in the topside N-channel
MOSFET, and level sensing for predictive delay circuit. Overcurrent is determined, when the topside N-channel MOS-
FET is on, by comparing the voltage on SW with respect to VDD and the voltage on the ILIM with respect to VDD.
This pin is also used for the return of the topside N-channel MOSFET driver.
Power input for the chip, 5.5-V maximum. Decouple close to the pin with a low-ESR capacitor, 1-碌F or larger.
ILIM
1
I
LDRV
6
O
SS/SD
4
I
SW
8
O
VDD
7
I
FUNCTIONAL BLOCK DIAGRAM
VDD
VDD
7
VDD
UVLO
ERROR AMPLIFIER
+
+
PWM COMP
HI
UVLO
OSC
0.65 V
3.7
碌A(chǔ)
SS/SD
4
SOFT
START
UVLO
SS ACTIVE
FAULT
COUNTER
DISCHARGE
0.26 V
SHUT DOWN
100 ns DELAY
EN
GND
5
CURRENT
LIMIT COMP
15
碌A(chǔ)
UDG鈭?3162
THERMAL
SHUTDOWN
LDRV
10
BOOT
2V
FB
2
0.7 V
REF
COMP
3
9
CLK
PWM
PREDICTIVE
GATE
DRIVE
HDRV
PWM
LOGIC
(VDD鈭?.2 V)
8
VDD
LO
6
LDRV
SW
FAULT
OC
1
ILIM
www.ti.com
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TPS40009

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