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TPS40007 Datasheet

  • TPS40007

  • 低輸入 (2.25V-5.5V) 300kHz 頻率的同步降壓控制器，具有輸出驅(qū)...

  • 26頁

  • TI

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TPS40007
TPS40009
SLUS589A鈭?NOVEMBER 2003 鈭?REVISED MAY 2004
APPLICATION INFORMATION
A shutdown feature can be implemented as shown in Figure 6. The device shuts down when the voltage at the
SS/SD pin falls below 260 mV. Because of this limitation, it is recommended that a MOSFET be used as the
controlling device, as in Figure 6. During shutdown, the total leakage current on the SW pin (I
SW
) is less than
2
碌A(chǔ).
When V
SS/SD
is greater than 290 mV, the device is enabled with normal SW active bias currents.
TPS40007/9
3.7
碌A(chǔ)
SS/SD
ERROR AMPLIFIER
4
C SS
SHUTDOWN
R
0.7 V
FB
+
+
COMP
SDN
0.26 V
+
UDG鈭?1163
Figure 6. Shutdown Implementation
Long soft start times may experience extended regions where the PWM pulse width is less than 100 ns. This
could lead to momentary overlap between HDRV and LDRV. As a result, there is a momentary increase in
ground or supply noise. It is important to ensure that the ground return of the synchronous rectifier be connected
directly to the ground return of the input bank of bypass capacitors, in order to minimize ground noise from
interfering with the controller during soft start. Also, if an external shutdown transistor is used in the application,
it is important to place a local bypass capacitor between its gate and source on the board in order to minimize
noise from interfering with the controller during soft-start.
OUTPUT PRE-BIAS
The TPS4000x supports pre-biased V
OUT
voltage applications. In cases, where the V
OUT
voltage is held up by
a pre-biasing supply while the controller is off, full synchronous rectification is disabled during the initial phase
of soft starting the V
OUT
voltage. When the first PWM pulses are detected during soft-start, the controller slowly
activates synchronous rectification by starting the first LDRV pulses with a narrow on-time. It then increments
that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1鈭扗), where D is the duty cycle
of the converter. This scheme prevents the initial sinking the pre-bias output, and ensures that the V
OUT
voltage
starts and ramps up smoothly into regulation. Note, if the V
OUT
voltage is pre-biased, PWM pulses start when
the error amplifier soft-start input voltage rises above the commanded FB voltage.
Figure 7 depicts the waveforms of the HDRV and LDRV output signals at the beginning PWM pulses. When
HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a short
pulse. With every cycle, the leading edge of LDRV is modulated, and the on-time of the synchronous rectifier
is increased. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve full
synchronous rectification.
At most, synchronous rectifier modulation takes place for the first 128 cycles after PWM pulses start. Note that
during the synchronous rectifier modulation region, the controller monitors pulse skipping. If the main HDRV
skips a pulse, the controller also skips a LDRV pulse. Pulse skipping could be experienced if the loop response
is much faster than the commanding soft-start ramp, especially when soft start times are long. The output
voltage ratchets up as the soft-start ramp catches up to it. Appropriate setting of loop response curbs this effect.
During normal regulation of the V
OUT
voltage, the controller operates in full two-quadrant source/sink mode.
12
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