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TPS40007 Datasheet

  • TPS40007

  • 低輸入 (2.25V-5.5V) 300kHz 頻率的同步降壓控制器，具有輸出驅...

  • 634.57KB

  • 26頁

  • TI

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TPS40007
TPS40009
SLUS589A鈭?NOVEMBER 2003 鈭?REVISED MAY 2004
APPLICATION INFORMATION
Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.
At time t0, power is applied to the converter. The voltage on the soft-start capacitor (V
CSS
) begins to ramp up.
At t1, the soft-start period is completed and the converter is regulating its output at the desired voltage level.
From t0 to t1, pulse-by-pulse current limiting is in effect, and from t1 onward, overcurrent pulses are counted
for purposes of determining a possible fault condition. At t2, a heavy overload is applied to the converter. This
overload is in excess of the overcurrent threshold. The converter starts limiting current and the output voltage
falls to some level depending on the overload applied. During the period from t2 to t3, the counter is counting
overcurrent pulses, and at time t3 reaches a full count of 7. The soft-start capacitor is then discharged, the
counter is decremented, and a fault condition is declared.
VDD
VCSS
~ 1.3 V
~ 0.6 V
0.6 V
FAULT
ILOAD
VOUT
t0
COUNTER
t1
0
t2 t3
6
t4
5
t5
4
t6
3
t7
2
t8
1
t9
t10
0
t
1 2 3 4 5 6 7
UDG鈭?3160
Figure 4. Overcurrent/Fault Waveforms
When the soft start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,
with a nominal 3.7-碌A current source. When the capacitor voltage crosses 1.3 V, it is discharged again and the
counter is decremented by one count. These transitions occur at t3 through t9. Not shown in Figure 4 is that
between t3 and t9, LDRV is maintained OFF. At t9, the counter has been decremented to 0. The fault logic is
then cleared, the outputs are enabled, and the converter attempts to restart with a full soft-start cycle. The
converter comes into regulation at t10.
10
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