Figure 9. Application Circuit
small PCB area. Additional design information is available
at www.ti.com.
at 1.8 V. R1, along with R2, R3, C1, C2, and C4 forms the
loop compensation network for the circuit. For this design,
a Type 3 topology is used.
In the application circuit, RT is grounded through a 71.5 k鈩?/div>
resistor to select the operating frequency of 700 kHz. To
set a different frequency, place a 68 k鈩?to 180 k鈩?resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default of 350 kHz. The resistance can
be approximated using the following equation:
INPUT FILTER
The input voltage is a nominal 5 VDC. The input filter C10
is a 10-碌F ceramic capacitor (Taiyo Yuden). C12, also a
10-碌F ceramic capacitor (Taiyo Yuden) provides high
frequency decoupling of the TPS54810 from the input
supply and must be located as close as possible to the
device. Ripple current is carried in both C10 and C12, and
the return path to PGND should avoid the current
circulating in the output capacitors C5, C7, and C8.
R
+
500 kHz
Switching Frequency
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 0.65-碌H inductor and
3 x 22-碌F capacitor. The inductor is a low dc resistance
(0.017
鈩?
type, Pulse Engineering PA0277. The
capacitors used are 22-碌F, 6.3 V ceramic types with X5R
dielectric. The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.
FEEDBACK CIRCUIT
The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R1 and R4 sets the output voltage for the circuit
8