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dsPIC33F Datasheet

  • dsPIC33F

  • High-Performance, 16-bit Digital Signal Controllers

  • 6105.68KB

  • 422頁(yè)

  • MICROCHIP   MICROCHIP

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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
8.0
AC/DC CHARACTERISTICS
AND TIMING REQUIREMENTS
Table 8-1 lists AC/DC characteristics and timing
requirements.
TABLE 8-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 鈥?0擄C-85擄C. Programming at 25擄C is recommended.
Param
Symbol
No.
D111
D112
D113
D031
D041
D080
D090
D012
D013
P1
P1A
P1B
P2
P3
P4
P4A
P5
P6
P7
P8
P9a
P9b
V
DD
I
PP
I
DDP
V
IL
V
IH
V
OL
V
OH
C
IO
C
F
T
PGC
T
PGCL
T
PGCH
T
SET
1
T
HLD
1
T
DLY
1
T
DLY
1
A
T
DLY
2
T
SET
2
T
HLD
2
T
DLY
3
T
DLY
4
T
DLY
5
Characteristic
Supply Voltage During Programming
Programming Current on MCLR
Supply Current During Programming
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Capacitive Loading on I/O pin (PGD)
Filter Capacitor Value on V
CAP
Serial Clock (PGC) Period
Serial Clock (PGC) Low Time
Serial Clock (PGC) High Time
Input Data Setup Time to Serial Clock
鈫?/div>
Input Data Hold Time from PGC
鈫?/div>
Delay between 4-bit Command and
Command Operand
Delay between Command Operand and
Next 4-bit Command
Delay between Last PGC
鈫?/div>
of Command
to First PGC
鈫?/div>
of Read of Data Word
V
DD
鈫?/div>
Setup Time to MCLR
鈫?/div>
Input Data Hold Time from MCLR
鈫?/div>
Delay between Last PGC
鈫?/div>
of Command
Byte to PGD
鈫?/div>
by Programming Executive
Programming Executive Command
Processing Time
Delay between PGD
鈫?/div>
by Programming
Executive to PGD Released by
Programming Executive
PGC Low Time After Programming
Bulk Erase Time
Page Erase Time
Row Programming Time
MCLR Rise Time to Enter ICSP mode
Data Out Valid from PGC
鈫?/div>
Delay between Last PGC
鈫?/div>
and MCLR
鈫?/div>
MCLR
鈫?/div>
to V
DD
鈫?/div>
Min
V
DDCORE
鈥?/div>
鈥?/div>
V
SS
0.8 V
DD
鈥?/div>
V
DD
鈥?0.7
鈥?/div>
1
136
40
40
15
15
40
40
20
100
25
12
10
15
Max
3.60
5
2
0.2 V
DD
V
DD
0.6
鈥?/div>
50
10
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
23
Units
V
渭A
mA
V
V
V
V
pF
渭F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
渭s
渭s
渭s
I
OL
= 8.5 mA @ 3.6V
I
OH
= -3.0 mA @ 3.6V
To meet AC specifications
Required for controller core
Conditions
Normal programming
(1)
P10
P11
P12
P13
P14
P15
P16
P17
T
DLY
6
T
DLY
7
T
DLY
8
T
DLY
9
T
R
T
VALID
T
DLY
10
T
HLD
3
400
200
20
1.5
鈥?/div>
10
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.0
鈥?/div>
鈥?/div>
100
ns
ms
ms
ms
渭s
ns
s
ns
Note 1:
V
DD
must also be supplied to the AV
DD
pins during programming. AV
DD
and AV
SS
should always be
within 鹵0.3V of V
DD
and V
SS
, respectively.
DS70152D-page 74
Preliminary
漏
2007 Microchip Technology Inc.

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