TC962
3.0
3.1
APPLICATIONS INFORMATION
Theory of Operation
internal to the TC962. Grounding pin 6 will turn on a
current source and double the frequency. This will
double the charge current going into the internal
capacitor, as well as any capacitor added to pin 7.
A zener diode has been added to the TC962 for use as
a reference in building external regulators. This zener
runs from pin 1 to ground.
The TC962 is a capacitive pump (sometimes called a
switched capacitor circuit), where four MOSFET
switches control the charge and discharge of a
capacitor.
The functional block diagram shows how the switching
action works. SW1 and SW2 are turned on simulta-
neously, charging C
P
to the supply voltage, V
IN
. This
assumes that the on resistance of the MOSFETs in
series with the capacitor results in a charging time
(3 time constants) that is less than the on time provided
by the oscillator frequency as shown:
3 (R
DS(ON)
C
P
) < C
P
/(0.5 f
OSC
)
In the next cycle, SW1 and SW2 are turned off and after
a very short interval of all switches being off (this
prevents large currents from occurring due to cross
conduction), SW3 and SW4 are turned on. The charge
in C
P
is then transferred to C
R
,
but with the polarity
inverted.
In this way, a negative voltage is now derived.
An oscillator supplies pulses to a flip-flop that is then
fed to a set of level shifters. These level shifters then
drive each set of switches at one-half the oscillator
frequency.
The oscillator has two pins that control the frequency of
oscillation. Pin 7 can have a capacitor added that is
returned to ground. This will lower the frequency of the
oscillator by adding capacitance to the timing capacitor
3.2
Latch Up
All CMOS structures contain a parasitic SCR. Care
must be taken to prevent any input from going above or
below the supply rail, or latch up will occur. The result
of latch up is an effective short between V
DD
and V
SS
.
Unless the power supply input has a current limit, this
latch up phenomena will result in damage to the device.
(See
AN763 Latch-up Protection of CMOS ICs.)
FIGURE 3-1:
690
TEST CIRCUIT
I
S
NC
+ 10碌F
C
P
1
2
3
4
8
7
I
L
C
OSC
5
R
L
V+
(+5V)
TC962
V
OUT
(鈥?V)
C
R
+
10碌F
FIGURE 3-2:
TYPICAL APPLICATIONS
Split V+ In Half
V+
1
V
D1
V
D2
V
OUT
= 鈥揤 +
C
R1
10碌F
C
R
+
10碌F
+
V
OUT
=
2V + 鈥?V
10碌F
V
OUT
=
V+
2
C
P
D
Combined Negative Converter and Positive Multiplier
V+
1
2
+ 10碌F 3
C
P2
4
C
P1
+
8
7
8
7
2
+
10碌F
3
4
TC962
6
5
+
TC962
6
5
Lowering Output Resistance by Paralleling Devices
V+
Positive Voltage Multiplier
V+
1
2
C
P1
+ 10碌F
3
4
8
7
+ 10碌F
1
2
C
P2
3
4
8
7
1
2
3
4
V
OUT
C
R
+
10碌F
8
7
V
D1
V
D2
C
P
+ 10碌F
C
P
+
10碌F
V
OUT
=
2V +鈥?V
TC962
6
5
TC962
6
5
TC962
6
5
D
錚?/div>
2002 Microchip Technology Inc.
DS21484B-page 5
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