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X40626 Datasheet

  • X40626

  • Dual Voltage CPU Supervisor with 64K Serial EEPROM

  • 516.51KB

  • XICOR   XICOR

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X40626
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X40626 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several bene鏗乼s.
鈥?It prevents the system microprocessor from starting
to operate with insuf鏗乧ient voltage.
鈥?It prevents the processor from operating prior to sta-
bilization of the oscillator.
鈥?It allows time for an FPGA to download its con鏗乬ura-
tion prior to initialization of the circuit.
鈥?It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
TRIP
threshold value
for t
PURST
(200ms nominal) the circuit releases
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the V
CC
level
and asserts RESET if supply voltage falls below a pre-
set minimum V
TRIP
. The RESET signal prevents the
microprocessor from operating in a power fail or brown-
out condition. The RESET signal remains active until
the voltage drops below 1V. It also remains active until
V
CC
returns and exceeds V
TRIP
for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL is HIGH (this is a start bit) prior to
the expiration of the watchdog time-out period to prevent
a RESET signal. The state of two nonvolatile control bits
in the Status Register determine the watchdog timer
period. The microprocessor can change these watchdog
bits, or they may be 鈥渓ocked鈥?by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any in-progress
communications are terminated. While RESET is
active, no new communications are allowed and no
non-volatile write operation can start. Non-volatile
writes in-progress when RESET goes active are
allowed to 鏗乶ish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
CC
/V
2MON
THRESHOLD RESET PROCEDURE
The X40626 is shipped with a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or if
higher precision is needed in the V
TRIP
value, the
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvola-
tile control signal.
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher or
lower voltage value. It is necessary to reset the trip
point before setting the new value.
The V
CC
and V2MON must be tied together during this
sequence.
Figure 1. Set V
TRIP
Level Sequence (V
CC
/V
2MON
= desired V
TRIP
values, WP = 12-15V when WEL bit set)
WP
V
P
= 12-15V
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
A0H
00H
xxH*
*for V
VTRIP2
address is 0DH
for V
TRIP
address is 01H
REV 1.1.15 2/11/04
00H
www.xicor.com
Characteristics subject to change without notice.
3 of 23

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