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UPD75206CW Datasheet

  • UPD75206CW

  • IC,MICROCONTROLLER,4-BIT,UPD75000 CPU,CMOS,SDIP,64PIN,PLASTI...

  • nec   nec

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碌
PD75206
Note
Mnemonic
SET1
Operands
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
No. of Machine
Bytes
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
鈥?/div>
2
2
2
2
2
2
2
2
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2+S
2
2
2
2
2
2
2
2
2
鈥?/div>
Operation
(mem.bit)鈫?
(fmem.bit)鈫?
(pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
))鈫?
(H+mem
3鈥?
.bit)鈫?
(mem.bit)鈫?
(fmem.bit)鈫?
(pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
))鈫?
(H+mem
3鈥?
.bit)鈫?
Skip if (mem.bit) = 1
Skip if (fmem.bit) = 1
Skip if (pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
)) = 1
Skip if (H+mem
3鈥?
.bit) = 1
Skip if (mem.bit) = 0
Skip if (fmem.bit) = 0
Skip if (pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
)) = 0
Skip if (H+mem
3鈥?
.bit) = 0
Skip if (fmem.bit) = 1 and clear
Skip if (pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
))=1 and clear
Skip if (H+mem
3鈥?
.bit)=1 and clear
CY鈫怌Y (fmem.bit)
CY鈫怌Y (pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
))
CY鈫怌Y (H+mem
3鈥?
.bit)
CY鈫怌Y (fmem.bit)
CY鈫怌Y (pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
))
CY鈫怌Y (H+mem
3鈥?
.bit)
CY鈫怌Y
CY鈫怌Y
CY鈫怌Y
(fmem.bit)
(pmem
7鈥?
+L
3鈥?
.bit(L
1鈥?
))
(H+mem
3鈥?
.bit)
Addressing
Area
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
Skip
Condition
CLR1
mem.bit
fmem.bit
pmem.@L
@H+mem.bit
SKT
mem.bit
fmem.bit
pmem.@L
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H+mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit)=1
Memory bit manipulation
@H+mem.bit
SKF
mem.bit
fmem.bit
pmem.@L
@H+mem.bit
SKTCLR
fmem.bit
pmem.@L
@H+mem.bit
AND1
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
OR1
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
XOR1
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
BR
addr
PC
12鈥?
鈫恆ddr
(Optimum instruction is
selected from among BR !addr,
BRCB !caddr and BR $addr by an
assembler.)
Branch
!addr
$addr
BRCB
BR
!caddr
PCDE
PCXA
3
1
2
2
2
3
2
2
3
3
PC
12鈥?
鈫恆ddr
PC
12鈥?
鈫恆ddr
PC
12鈥?
鈫怭C
12
+caddr
11鈥?
PC
12鈥?
鈫怭C
12鈥?
+DE
PC
12鈥?
鈫怭C
12鈥?
+XA
*6
*7
*8
Note
Instruction Group
32

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