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UPD75206CW Datasheet

  • UPD75206CW

  • IC,MICROCONTROLLER,4-BIT,UPD75000 CPU,CMOS,SDIP,64PIN,PLASTI...

  • nec   nec

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碌
PD75206
5.2
CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control register (PPC) and
system clock control register (SCC).
This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.
鈥?/div>
0.95
碌
s, 1.91
碌
s, 15.3
碌
s (main system clock: 4.19 MHz)
鈥?/div>
122
碌
s (subsystem clock: 32.768 kHz)
Fig. 5-1 Clock Generator Block Diagram
XT1
Subsystem
Clock
Generator
f
XT
Watch Timer
Timer/Pulse
Generator
Main System
Clock
Generator
Selector
1/8~1/4096
f
XX
Frequency Divider
1/2 1/6
SCC
SCC3
Selector
SCC0
PCC
Internal Bus
PCC0
Oscillation
Stop
Frequency
Divider
1/4
鈥?FIP Controller
鈥?Basic Interval Timer (BT)
鈥?Timer/Event Counter
鈥?Serial Interface
鈥?Watch Timer
鈥?INT0 Noise Eliminator
XT2
X1
X2
f
X
桅
鈥?CPU
鈥?INT0 Noise Eliminator
鈥?INT1 Noise Eliminator
PCC1
4
HALT F/F
HALT*
STOP*
PCC2
PCC3
R
Q
S
PCC2 and
PCC3
Clear
STOP F/F
Q
S
Wait Release Signal from BT
RES Signal (Internal Reset)
R
Standby Release Signal from
Interrupt Control Circuit
*
Instruction execution
1.
2.
3.
4.
5.
6.
7.
f
X
= Main system clock frequency
f
XT
= Subsystem clock frequency
f
XX
= System clock frequency
Remarks
桅
= CPU clock
PCC: Processor clock control register
SCC: System clock control register
1 clock cycle (t
CY
) of
桅
is 1 machine cycle of an instruction. For t
CY
, see 鈥滱C Characteristics鈥?in
12.
ELECTRICAL SPECIFICATIONS.
15
5

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