鈭?/div>
R2
Bandgap
Reference
CNTRL
(3)
LOGIC
BLOCK
GND
(2)
Figure 2. Detailed Block Diagram
PIN FUNCTION DESCRIPTIONS
Pin #
1
Symbol
OUT
Pin Description
This signal drives the gate of a P鈭抍hannel MOSFET. It is controlled by the voltage level on IN or the logic state of
the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of V
CC
in less
than 1.0
msec
provided that gate and stray capacitance is less than 12 nF.
Circuit Ground
This logic signal is used to control the state of OUT and turn鈭抩n/off the P鈭抍hannel MOSFET. A logic High results
in the OUT signal being driven to within 1.0 V of V
CC
which disconnects the FET. The input is tied Low via an
internal 50 kW pull鈭抎own resistor. It is recommended that the input be connected to GND if it is not used.
This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (V
th
),
the OUT pin will be driven to within 1.0 V of V
CC
, thus disconnecting the FET. The nominal threshold level can be
increased with the addition of an external resistor divider between IN, V
CC
, and GND.
Positive Voltage supply. OUT is guaranteed to be in low state (MOSFET ON) as long as V
CC
remains above
2.5 V, and below the overvoltage threshold.
2
3
GND
CNTRL
4
IN
5
V
CC
TRUTH TABLE
IN
<V
th
<V
th
>V
th
>V
th
CNTRL
L
H
L
H
OUT
GND
V
CC
V
CC
V
CC
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