IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
6.42
13
t
OLZ
t
CLZ
O1(Ax)
OE
(Burst wraps around
to its initial state)
t
CHZ
O4(Ay)
O1(Ay)
O2(Ay)
DATA
OUT
Output
Disabled
Pipelined
Read
Burst Pipelined Read
5297 drw 08
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO
input.
2. ZZ input is LOW and
LBO
is Don't Care for this cycle.
3. CS
0
timing transitions are identical but inverted to the
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
