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IDT7130LA Datasheet

  • IDT7130LA

  • HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

  • IDT

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IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(3)
t
ACE
t
AOE
(4)
t
HZ
(2)
t
LZ
DATA
OUT
t
LZ
I
CC
CURRENT
I
SS
t
PU
50%
(1)
(1)
t
HZ
VALID DATA
t
PD
(4)
(2)
50%
2689 drw 09
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is deaserted first,
OE
or
CE
.
3. R/
W
= V
IH
and the address is valid prior to or coincidental with
CE
transition Low.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
, and t
BDD
.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(5)
7130X20
(2)
7130X25
(6)
Symbol
Parameter
Write Cycle
Write Cycle Time
(3)
t
WC
t
EW
Chip Enable to End-of-Write
Address Valid to End-of-Write
t
AW
t
AS
Address Set-up Time
Write Pulse Width
(4)
t
WP
t
WR
Write Recovery Time
Data Valid to End-of-Write
t
DW
t
HZ
Output High-Z Time
(1)
Data Hold Time
t
DH
t
WZ
Write Enabled to Output in High-Z
(1)
Output Active From End-of-Write
(1)
t
OW
Min.
20
15
15
0
15
0
10
鈥?/div>
0
鈥?/div>
0
7140X25
(6)
Max. Min. Max.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
10
鈥?/div>
10
鈥?/div>
25
20
20
0
15
0
12
鈥?/div>
0
鈥?/div>
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
10
鈥?/div>
10
鈥?/div>
7130X35
7130X55
7130X100
7140X100
Min. Max.
100
90
90
0
55
0
40
鈥?/div>
0
鈥?/div>
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
40
鈥?/div>
40
鈥?/div>
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7140X35
7140X55
Min. Max. Min. Max.
35
30
30
0
25
0
15
鈥?/div>
0
鈥?/div>
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
15
鈥?/div>
15
鈥?/div>
55
40
40
0
30
0
20
鈥?/div>
0
鈥?/div>
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
25
鈥?/div>
25
鈥?/div>
NOTES:
2689 tbl 10
1. Transition is measured
鹵500mV
from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. 0擄C to +70擄C temperature range only, PLCC and TQFP packages.
3. For MASTER/SLAVE combination, t
WC
= t
BAA
+ t
WP
, since R/
W
= V
IL
must occur after t
BAA.
4. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
5. 鈥淴鈥?in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
6.01
7

IDT7130LA PDF文件相關(guān)型號

IDT7130SA,IDT7140LA,IDT7140SA

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