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IDT7130LA Datasheet

  • IDT7130LA

  • HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

  • IDT

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IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I 鈥?NON-CONTENTION
READ/WRITE CONTROL
(4)
Left or Right Port
(1)
R/
D
0鈥?
CE OE
X
H
X
Z
W
X
L
H
H
H
L
L
L
X
X
L
H
Z
DATA
IN
DATA
OUT
Z
Function
Port Disabled and in Power-
Down Mode, I
SB2
or I
SB4
CE
R
=
CE
L
=
V
IH
, Power-Down
Mode, I
SB1
or I
SB3
Data on Port Written Into Memory
(2)
Data in Memory Output on Port
(3)
High Impedance Outputs
NOTES:
2689 tbl 13
1. A
0L
鈥?A
10L
鈮?/div>
A
0R
鈥?A
10R
.
2. If
BUSY
= L, data is not written.
3. If
BUSY
= L, data may not be valid, see t
WDD
and t
DDD
timing.
4. 'H' = V
IH
, 'L' = V
IL
, 'X' = DON鈥橳 CARE, 'Z' = HIGH IMPEDANCE
TABLE II 鈥?INTERRUPT FLAG
(1,4)
R/
W
L
L
X
X
X
CE
L
L
X
X
L
Left Port
OE
L
X
X
X
L
A
9L
鈥?A
0L
3FF
X
X
3FE
INT
L
X
X
L
(3)
H
(2)
R/
W
R
X
X
L
X
CE
R
X
L
L
X
Right Port
OE
R
X
L
X
X
A
9L
鈥?A
0R
X
3FF
3FE
X
INT
R
L
H
(3)
X
X
(2)
Function
Set Right
INT
R
Flag
Reset Right
INT
R
Flag
Set Left
INT
L
Flag
Reset Left
INT
L
Flag
2689 tbl 14
NOTES:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
2. If
BUSY
L
= V
IL
, then No Change.
3. If
BUSY
R
= V
IL
, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON鈥橳 CARE
TABLE III 鈥?ADDRESS BUSY ARBITRATION
Inputs
Outputs
CE
L
X
H
X
L
CE
R
X
X
H
L
A
0L
-A
9L
A
0R
-A
9R
NO MATCH
MATCH
MATCH
MATCH
BUSY
L(1)
BUSY
R(1)
H
H
H
(2)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit
(3)
NOTES:
2689 tbl 15
1. Pins
BUSY
L
and
BUSY
R
are both outputs for IDT7130 (master). Both are
inputs for IDT7140 (slave).
BUSY
X
outputs on the IDT7130 are open drain,
not push-pull outputs. On slaves the
BUSY
X
input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either
BUSY
L
or
BUSY
R
= Low will result.
BUSY
L
and
BUSY
R
outputs can
not be low simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
BUSY
R
outputs are driving Low regard-
less of actual logic level on the pin.
6.01
12

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IDT7130SA,IDT7140LA,IDT7140SA

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